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Improving Code Density with Variable Length Encoding Aware Instruction Scheduling

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Abstract

Variable length encoding can considerably decrease code size in VLIW processors by reducing the number of bits wasted on encoding No Operations(NOPs). A processor may have different instruction templates where different execution slots are implicitly NOPs, but all combinations of NOPs may not be supported by the instruction templates. The efficiency of the NOP encoding can be improved by the compiler trying to place NOPs in such way that the usage of implicit NOPs is maximized. Two different methods of optimizing the use of the implicit NOP slots are evaluated: (a) prioritizing function units that have fewer implicit NOPs associated with them and (b) a post-pass to the instruction scheduler which utilizes the slack of the schedule by rescheduling operations with slack into different instruction words so that the available instruction templates are better utilized. Three different methods for selecting basic blocks to apply FU priorization on are also analyzed: always, always outside inner loops, and only outside inner loops only in basic blocks after testing where it helped to decrease code size. The post-pass optimizer alone saved an average of 2.4 % and a maximum of 10.5 % instruction memory, without performance loss. Prioritizing function units in only those basic blocks where it helped gave the best case instruction memory savings of 10.7 % and average savings of 3.0 % in exchange for an average 0.3 % slowdown. Applying both of the optimizations together gave the best case code size decrease of 12.2 % and an average of 5.4 %, while performance decreased on average by 0.1 %.

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Acknowledgments

This work was funded by Academy of Finland (funding decision 253087), Finnish Funding Agency for Technology and Innovation (project ”Parallel Acceleration”, funding decision 40115/13), and ARTEMIS Joint Undertaking under grant agreement no 621439 (ALMARVI).

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Authors and Affiliations

  1. Tampere University of Technology, Tampere, Finland

    Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala & Jarmo Takala

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  1. Heikki Kultala
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  2. Timo Viitanen
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  3. Pekka Jääskeläinen
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  4. Janne Helkala
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  5. Jarmo Takala
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Correspondence to Heikki Kultala.

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Kultala, H., Viitanen, T., Jääskeläinen, P. et al. Improving Code Density with Variable Length Encoding Aware Instruction Scheduling. J Sign Process Syst 84, 435–446 (2016). https://doi.org/10.1007/s11265-015-1081-6

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  • DOI: https://doi.org/10.1007/s11265-015-1081-6

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