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Designs of Low Power Snoop for Multiprocessor System on Chip

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Abstract

In multiprocessor system on chip, processors can access expectable shared data by using snoop protocol in different time. However, this design will generate a large number of snoops to consume unnecessary energy. The main objective of the paper is to reduce the number of snoops of the multiprocessor system by using an energy-saving architecture. The proposed method includes two designs: 1) snoop turning point design and 2) snoop buffer design. In the first design, a main key defined as the critical section in which the data accessed synchronously by multiple processors is presented. When the data in critical section are accessed by a processor, the critical section will be locked immediately such that other processors cannot access the data. Because the critical section processors have not common accessing data with the other processors, all snoops are removed after snooping turning point. In the second design, we add buffers to the caches and shared buses to label the number of common data processors. Using the design, only the processors labeled in buffers need to be snooped. The experimental results are shown that the proposed designs can achieve the purpose of energy saving.

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Authors and Affiliations

  1. Department of Computer and Information Science and Engineering, National University of Tainan, Tainan, Taiwan

    Chi-Chou Kao & Yi-Ciang Lin

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  1. Chi-Chou Kao
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  2. Yi-Ciang Lin
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Correspondence to Chi-Chou Kao.

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Kao, CC., Lin, YC. Designs of Low Power Snoop for Multiprocessor System on Chip. J Sign Process Syst 88, 83–89 (2017). https://doi.org/10.1007/s11265-016-1135-4

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  • DOI: https://doi.org/10.1007/s11265-016-1135-4

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