Abstract
CORDIC is a simple algorithm that uses adders and shifters to compute elementary functions. CORDIC has wide applications because of its low resource consumption and simple hardware architecture. CORDIC traditionally dedicates calculation units only for integer or fixed-point number. Control scheme and structure are also complicated. In this paper, we propose a floating-point elementary function computing method combined with dedicated circuits and floating-point arithmetic components. The arithmetic components minimize hardware resource and enhance flexibility. Dedicated circuits improve computing speed and simplify hardware structure. The floating-point elementary function processor can be easily designed using the method described. And FPU can be modified to have the capability of elementary function computing. A double precision floating-point elementary function processor with a simple and flexible structure is designed. A single precision processor is implemented with an FPGA and synthesized with Synopsys Design Compiler. Synthesis and experimental results show that the processor can calculate all the common elementary functions. The processor has merits of simple structure and design, flexibility, and wide application range.








Similar content being viewed by others
References
Lee, D., Cheung, R., Luk, W., & Villasenor, J. (2008). Hardware implementation trade-offs of polynomial approximations and interpolations. IEEE Transactions on Computers, 57(5), 686– 701.
Low, J., & Jong, C. (2013). A memory-efficient tables-and-additions method for accurate computation of elementary functions. IEEE Transactions on Computers, 62(5), 858–872.
James, E., & Schulte, J. (1999). The symmetric table addition method for accurate function approximation. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 21(2), 167–177.
Blythe, D. (2008). Rise of the graphics processor. Proceedings of the IEEE, 96(5), 761–778.
Maharatna, K., Dhar, A., & Banerjee, S. (2001). A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Processing, 81(9), 1813–1822.
Aggarwal, S., Meher, P., & Khare, K. (2013). Scale-free hyperbolic CORDIC processor and its application to waveform generation. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(2), 314–326.
Andraka, R. (1998). A survey of CORDIC algorithms for FPGA based computers. In Proceedings of the 1998 ACM/SIGDA 6th international symposium on Field programmable gate arrays (pp. 191–200).
Schulte, M., & Swartzlander, E. (1994). Hardware designs for exactly rounded elementary functions. IEEE Transactions on Computers, 43(8), 964–973.
Kantabutra, V. (1996). On hardware for computing exponential and trigonometric functions. IEEE Transactions on Computers, 45(3), 328–339.
Paliouras, V., Karagianni, K., & Stouraitis, T. (2000). A floating-point processor for fast and accurate sine/cosine evaluation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(5), 441–451.
Hsiao, S., Ko, H., & Wen, C. (2012). Two-level hardware function evaluation based on correction of normalized piecewise difference functions. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(5), 292–296.
Vazquez, A., & Bruguera, J. (2013). Iterative algorithm and architecture for exponential, logarithm, powering, and root extraction. IEEE Transactions on Computers, 62(9), 1721–1731.
Hu, Y. (1992). CORDIC-based VLSI architectures for digital signal processing. IEEE Signal Processing Magazine, 9(3), 16–35.
Rupley, J., King, J., Quinnell, E., Galloway, F., Patton, K., Seidel, P., Dinh, J., Bui, H., & Bhowmik, A. (2013). The floating-point unit of the jaguar x86 core. In IEEE symposium on computer arithmetic (pp. 7–16).
Volder, J. (1959). The CORDIC trigonometric computing technique. IRE Transactions on Electronic Computers, 8(3), 330–334.
Volder, J. (2000). The birth of CORDIC. Journal of VLSI Signal Processing, 25(2), 101–105.
Hwang, Y., Chen, W., & Hong, C. (2014). A low complexity geometric mean decomposition computing scheme and its high throughput VLSI implementation. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(4), 1170–1182.
Maharatna, K., Dhar, A.S., & Banerjee, S. (2001). A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Processing, 81(9), 1813–1822.
Acharyya, A., Maharatna, K., Al-Hashimi, B., & Reeve, J. (2011). Co-ordinate rotation based low complexity N-D FastICA algorithm and architecture. IEEE Transactions on Signal Processing, 59(8), 3997–4011.
Meher, P., & Park, S. (2013). CORDIC designs for fixed angle of rotation. IEEE Transactions on Very Large Scale Integration Systems, 21(2), 217–228.
Lang, T., & Antelo, E. (2005). High-throughput CORDIC-based geometry operations for 3D computer graphics. IEEE Transactions on Computers, 54(3), 347–361.
Lee, M., Yoon, J., & Park, J. (2014). Reconfigurable CORDIC-based low-power DCT architecture based on data priority. IEEE Transactions on Very Large Scale Integration Systems, 22(5), 1060–1068.
Walther, J. (1971). A unified algorithm for elementary functions. In Proceedings of spring joint computer conference (pp. 379–385).
Meher, P., Valls, J., Juang, T., Sridharan, K., & Maharatna, K. (2009). Fifty years of CORDIC: algorithms, architectures, and applications. IEEE Transactions on Circuits and Systems-I, 56(9), 1893–1907.
Antelo, E., Villalba, J., Bruguera, J., & Zapatai, E. (1997). High performance rotation architectures based on the radix-4 CORDIC algorithm. IEEE Transactions on Computers, 46(8), 855–870.
Synopsys, Inc. (2010). DesignWare building block IP documentation overview.
Acknowledgments
This work is supported by Project funded by China Postdoctoral Science Foundation (2014M550492) and National Natural Science Foundation of China (61231018 and 61273366).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Zhang, B., Zhao, J. Elementary Function Computing Method for Floating-Point Unit. J Sign Process Syst 88, 311–321 (2017). https://doi.org/10.1007/s11265-016-1166-x
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-016-1166-x