Abstract
The invention of Polar codes by Arıkan is a major breakthrough in coding theory. Polar Code decoding algorithm implementation is a major challenge to recover transmitted information. Thus, several polar decoder architectures were proposed in the literature. All of these architectures focused on reducing the computational hardware complexity and increasing the throughput of polar decoders. However, the memory requirements remain a limiting implementation factor that has not been fully adressed yet. This paper proposes a novel method to simply redesign existing decoder architectures in order to use less memory at the cost of some extra computational logic. The main idea is to replace memory sections — assigned to store intermediate results — with computational logic. The method, applied to an existing decoder \(\mathcal {D}\), results in what is called a mixed decoder architecture based on \(\mathcal {D}\), denoted \(M({\mathcal {D}})\). Since previous decoders are based on the semi-parallel decoder architecture, we first apply the memory requirement reduction technique to a semi-parallel decoder. Analyses, together with logic synthesis results, show that the gains brought by the reduction in memory area requirements are well worth the induced extra computational logic area. We show that the memory requirement reduction technique can increase the speed/area ratio by 25 % when implemented in standard cell technology (ST 65 nm). We also provide some insights on the potential gain that this method would provide on state-of-the-art decoders implemented on FPGA devices. For example, it is shown that the proposed method can lower the decoder memory requirements by 50 % while using less than 20 % of the FPGA logic elements, and implying a latency penalty of less than 5 %.













Similar content being viewed by others
Notes
1 A node is updated when both its LLRs and partial sums have been updated. SC Decoding Algorithm is completed when the root node has been updated.
Table 1 Decoding process scheduling for N=16 as described in Fig. 3.
References
5g: A technology vision. http://www.huawei.com/5gwhitepaper/, Accessed: 2010-09-30.
Alamdar-Yazdi, A., & Kschischang, F.R. (2011). A simplified successive-cancellation decoder for polar codes. IEEE Communications Letters, 15(12), 1378–1380.
Arikan, E. (2008). Channel polarization: A method for constructing capacity-achieving codes. In IEEE ISIT 2008 (pp. 1173–1177).
Arikan, E. (2009). Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels. IEEE Transactions on Information Theory, 55(7), 3051–3073.
Berhault, G., Leroux, C., Jego, C., & Dallet, D. Partial sums generation architecture for successive cancellation decoding of polar codes. In IEEE workshop on signal processing systems (SiPS), 2013 (pp. 407–412): IEEE.
Berhault, G., Leroux, C., Jego, C., & Dallet, D. (2015). Partial sums computation in polar codes decoding. In IEEE international symposium on circuits and systems (ISCAS), 2015 (pp. 826–829).
Chen, K., Niu, K., & Lin, J.R. (2012). List successive cancellation decoding of polar codes. Electronics Letters, 48(9), 500–501.
Fan, Y., & Tsui, C.Y. (2014). An efficient partial-sum network architecture for semi-parallel polar codes decoder implementation. IEEE Transactions on Signal Processing, 62(12), 3165–3179.
Giard, P., Sarkis, G., Thibeault, C., & Gross, W.J. (2015). 237 gbit/s unrolled hardware polar decoder. Electronics Letters, 51(10), 762–763.
Leroux, C., Raymond, A.J., Sarkis, G., & Gross, W.J. (2013). A semi-parallel successive-cancellation decoder for polar codes. IEEE Transactions on Signal Processing, 61(2), 289–299.
Leroux, C., Raymond, A.J., Sarkis, G., Tal, I., Vardy, A., & Gross, W.J. (2012). Hardware implementation of successive-cancellation decoders for polar codes. Journal of Signal Processing Systems, 69(3), 305–315.
Leroux, C., Tal, I., Vardy, A., & Gross, W.J. (2011). Hardware architectures for successive cancellation decoding of polar codes, (pp. 1665–1668).
Li, B., Shen, H., & Tse, D. (2012). An adaptive successive cancellation list decoder for polar codes with cyclic redundancy check. IEEE Communications Letters, 16(12), 2044–2047.
Pamuk, A., & Arikan, E. A two phase successive cancellation decoder architecture for polar codes. In 2013 IEEE international symposium on information theory proceedings (ISIT) (pp. 957–961).
Raymond, A.J., & Gross, W.J. (2014). A scalable successive-cancellation decoder for polar codes. IEEE Transactions on Signal Processing, 62(20), 5339–5347.
Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W.J. (2014). Fast polar decoders: Algorithm and implementation. IEEE Journal on Selected Areas in Communications, 32(5), 946–957.
Sasoglu, E., Telatar, E., & Arikan, E. (2009). Polarization for arbitrary discrete memoryless channels. In Information theory workshop, 2009. ITW 2009 (pp. 144–148): IEEE.
Tal, I., & Vardy, A. (2015). List decoding of polar codes. IEEE Transactions on Information Theory, 61(5), 2213–2226.
Zhang, C., & Parhi, K. (2013). Low-latency sequential and overlapped architectures for successive cancellation polar decoder. IEEE Transactions on Signal Processing, 61(10), 2429–2441.
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
About this article
Cite this article
Berhault, G., Leroux, C., Jego, C. et al. Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes. J Sign Process Syst 88, 425–438 (2017). https://doi.org/10.1007/s11265-016-1179-5
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-016-1179-5