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Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design

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An Author Correction to this article was published on 18 February 2020

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Abstract

Error concealment (EC) can recover visual quality, while transmission error occurs on video bitstream. Generally, EC is an extra function integrated into the video decoder and also consumes an additional hardware resource. It’s hardware architecture is only activated, when transmission error occurs. Otherwise, it is totally idle, causing a poor hardware utilization. To overcome this problem, the MC-Reused SEC algorithm is proposed. It makes the arithmetic operations of EC compliant with those of MC. This indicates arithmetic operations can be shared with each other. Both MC and EC can be processed on an identical hardware architecture instead of individual ones. Consequently, the limitation on hardware utilization for joint MC and EC can be eliminated. This work has proposed a hardware architecture that can be fully-shared between MC and EC with a 100 % hardware utilization. This hardware architecture can demonstrate a higher hardware efficiency, which considers power, gate count, and throughput. Moreover, the hardware-sharing can also increase the cost-efficiency especially for more advanced process technologies. This work is realized with the technology of TSMC 0.18um CMOS process. The throughputs of MC and EC are 1.0 Gpixels/sec and 320 Mpixels/sec, respectively. Experiment results reveal that this work demonstrates a competitive performance on hardware-efficiency.

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Change history

  • 18 February 2020

    I am the author of this paper published in Journal of Signal processing Systems.

  • 18 February 2020

    I am the author of this paper published in Journal of Signal processing Systems.

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Acknowledgments

This work was supported in part by Military of Science Technology (MOST), under Grant MOST 103-2221-E-155-073. Many thanks for MOST and Chip Implementation Center (CIC) for their financial-support and IC design tool-support.

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  1. Electrical Engineering/Innovation Center for Big Data and Digital Convergence, Yuan-Ze University, 135 Yuan-Tung Road, Chung-Li, 32003, Taoyuan, Taiwan, People’s Republic of China

    Yu-Hsuan Lee & Bo-Siang Huang

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  1. Yu-Hsuan Lee
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  2. Bo-Siang Huang
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Correspondence to Yu-Hsuan Lee.

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Lee, YH., Huang, BS. Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design. J Sign Process Syst 89, 319–333 (2017). https://doi.org/10.1007/s11265-016-1196-4

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  • DOI: https://doi.org/10.1007/s11265-016-1196-4

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