Skip to main content
SpringerLink
Log in

A High Throughput JPEG2000 Entropy Decoding Unit Architecture

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper is dedicated to a hardware architecture development for JPEG2000 entropy decoding unit (EDU) which consist of two parts: context modeling unit (CMU) and arithmetic decoding unit (ADU). To achieve a high throughput we propose an efficient pixel skipping scheme to save clock cycles for non-context position in CMU and realize the ADU logic by combinational circuit to keep the result of ADU within the same clock of context which can reduce the latency to zero clock cycle between CMU and ADU. We show that the proposed EDU architecture attains a throughput of 68.66–232.14 Mbps for a single decoding core depending on compression ratios, and consumes 95.79 mW based on SMIC 0.13 um technology. In comparison with the state-of-the-art decoders the proposed EDU architecture provides consistent reconstruction performance with software decoder and comparable throughput, memory and power consumption.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. ITU-T and ISO/IEC JTC 1 (2000). “JPEG 2000 Image Coding System: Core Coding System, ITU-T Recommendation T.800 and ISO/IEC 15444–1,” JPEG 2000 Part 1.

  2. Xu, R.X., Tie, X., Chao, X., (2010). “A High-Performance JPEG2000 Decoder Based on FPGA According to DCI Specification,” Photonics and Optoelectronic, 2010 Symposium on, 1–4.

  3. Jimenez-Rodriguez, L., Auli-Llinas, F., & Marcellin, M. W. (2014). Visually lossless strategies to decode and transmit JPEG2000 imagery. IEEE Signal Processing Letters, 21(1), 35–38.

    Article  Google Scholar 

  4. Jimenez-Rodriguez L., Auli-Llinas F., Marcellin M.W., Serra-Sagrista J., (2013). Visually Lossless JPEG 2000 Decoder. Data Compression Conference (DCC), 161–170.

  5. Descampe, A., Member, S., & Devaux, F. O. (2006). A flexible hardware JPEG 2000 decoder for digital cinema. IEEE Transactions on Circuits and Systems for Video Technology, 16(11), 1397–1410.

    Article  Google Scholar 

  6. Descampe, A., Devaux, F.O., Rouvroy,G., Macq, B. and Legat, J.D., (2004). “An Efficient FPGA Implementation of a Flexible JPEG2000 Decoder For Digital Cinema,” Signal Processing Conference, 2004 12th European, 2019–2022.

  7. Gupta, A., Nooshabadi, S., & Taubman, D. (2005). The high throughput bit plane decoder for JPEG2000 based on selective sample skipping algorithm. Circuits and Systems, 2005. 48th Midwest Symposium on, 2, 1434–1437.

    Article  Google Scholar 

  8. Dyer, M., Nooshabadi, S., & Taubman, D. (2005). Reduced latency arithmetic decoder for JPEG2000 block decoding. IEEE International Symposium on Circuits and Systems (ISCAS 2005), 3, 2076–2079.

    Article  Google Scholar 

  9. Dyer, M., Taubman, D., Nooshabadi, S., & Gupta, A. (2006). Concurrency techniques for arithmetic coding in JPEG2000. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(6), 1203–1213.

    Article  Google Scholar 

  10. Lucking, D. J., Balster, E. J., Hill, K. L., & Scarpino, F. A. (2013). FPGA implementation of the JPEG2000 binary arithmetic decoder. Journal of Real-Time Image Processing, 8, 411–419.

    Article  Google Scholar 

  11. Lucking, D.J., Balster, E.J., (2010). “An Increased Throughput FPGA Design of the JPEG2000 Binary Arithmetic Decoder,” Digital Image Computing: Techniques and Applications,2010 International Conference on, 400–405.

  12. Le R., Mundy J.L., Bahar R.I. (2012). “High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System,” IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 16–23.

  13. Barco-Silex, “JPEG2000 Decoder: BA111JPEG2000D Factsheet,” [Online], Available: http://www.barco.com.

  14. CAST, ``JPEG (2000) Compression Encoder Core,” [Online] , Available: http://www.cast-inc.com/ip-cores/images/jpeg2k-e/index.html.

  15. intoPIX, “HD JPEG (2000) Encoders and Decoders IP-cores,” [Online], Available: http://www.intopix.com.

  16. Taubman, D. (2000). High performance scalable image compression with EBCOT. IEEE Transaction on Image Processing, 9(7), 1158–1170.

    Article  Google Scholar 

  17. Grzegorz, P. (2005). A high performance architecture for embedded block coding in JPEG2000. IEEE Transactions on Circuits and Systems for Video Technology, 15(9), 1182–1191.

    Article  Google Scholar 

  18. Moinuddin, A. A., Khan, E., & Ghanbari, M. (2008). Efficient algorithm for very low bit rate embedded image coding. IET Image Processing, 2(2), 59–71.

    Article  MathSciNet  Google Scholar 

  19. Kosheleva, O. M., Usevitch, B. E., Cabrera, S. D., & Vidal, E. (2006). Rate distortion optimal bit allocation methods for volumetric data using JPEG 2000. IEEE Transactions on Image Processing, 15(8), 2106–2112.

    Article  Google Scholar 

  20. Horrigue L., Saidani T., Ghodhbane R., Atri M. (2014). “A high performance MQ decoder architecture in JPEG2000,” World Congress on Computer Applications and Information Systems (WCCAIS), 1–5.

  21. Zezza S., Masera G., Nooshabadi S. (2014). “A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic,” IEEE International Symposium on Circuits and Systems (ISCAS), 902–905.

  22. Hsin, H.C., Sung, T.Y., Shieh, Y.S., (2012). “A fast MQ table based merging algorithm for image segmentation,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 1009–1012.

  23. Kulkarni, O.C., Sarawadekar, K., Banerjee, S., (2011). “VLSI Implementation of MQ Decoder in JPEG2000,” Proceeding of the 2011 IEEE Students' Technology Symposium, 193–197.

Download references

Acknowledgements

This research work is supported by the National Natural Science Foundation of China under Grant No. 61571345, 91538101, 61850410523 and Huawei Innovation Research Program under Grant No.2017050310. The authors would like to thank the reviewers for their helpful comments and criticism.

Author information

Authors and Affiliations

  1. School of computer science and technology, XIDIAN University, Xi’an, China

    Kai Liu & YunSong Li

  2. Information Systems Department, ITMO University, St. Petersburg, Russia

    Evgeny Belyaev

Authors
  1. Kai Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Evgeny Belyaev
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. YunSong Li
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kai Liu.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Liu, K., Belyaev, E. & Li, Y. A High Throughput JPEG2000 Entropy Decoding Unit Architecture. J Sign Process Syst 91, 899–913 (2019). https://doi.org/10.1007/s11265-018-1411-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-018-1411-6

Keywords

Search

Navigation