The Design and Implementation of a Highly Efficient and Low-Complexity Joint-MMSE GFDM Receiver

Abstract

This paper presents the VLSI architecture of a highly-efficient and low-complexity Generalized Frequency Division Multiplexing (GFDM) receiver based on the joint Minimum Mean Square Error (joint-MMSE) approach. To be specific, a novel data processing flow is proposed in this paper where the bit reverse permutation after the FFT operation and the shuffle permutation are conducted concurrently. As a result, the processing delay is greatly reduced and the memory requirement for the temporary storage is saved. Based on the designed data flow, the VLSI architecture of the joint-MMSE GFDM receiver is presented. A novel folded structure is proposed so that the arithmetic and storage elements are utilized in a time-sharing manner and the area complexity is decreased. These elements are also architected with high configurability to support various processing modes. Moreover, a novel memory-access algorithm and address-generation circuit is designed to efficiently access the memory module and to mitigate the data conflict when supporting different processing modes. The proposed design is synthesized using TSMC 90 nm technology at operating frequency of 200 MHz. The post-synthesis estimation shows that this architecture occupies an area complexity of 492.6 kGEs. The analyses results illustrate that the proposed data flow leads to a 16% reduction in delay and complexity compared to the conventional approaches. Furthermore, the proposed design enhances the Efficiency by 4.7x compared to the state of the art work.