Abstract
Non-Destructive Evaluation/Testing (NDE/NDT) is comprised of advanced sensor technologies that can evaluate structures, materials and components for defects and analyze their properties. In recent years, researchers have been applying deep learning algorithms on NDT technologies to improve the capability of detecting and classifying complex sensor data. However, deep learning models often require large computational resources including specialized hardware accelerators, dedicated memory blocks and increased power consumption. It is very challenging to implement these deep learning algorithms in real-time testing scenarios in the field due to limited access to aforementioned computational resources. To address this issue, we introduce a model compression algorithm and the corresponding Field Programmable Gate Array (FPGA) accelerators for a novel deep learning model targeting ultrasonic NDT techniques. The ultrasonic deep learning algorithm which is based on Meta Learning is capable of detecting and classifying different flaw types (e.g. cracks, holes) within the specimen. The results have shown that the model compression has significantly reduced the required operations with minimal accuracy loss, and the low-cost FPGA hardware platform is able to accelerate the inference using compressed model with high efficiency.













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Data that support the findings of this study are available upon reasonable request from the corresponding author (E.O.).
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Yu Yuan is primarly responsible for the hardware realization and model compression methods. Kushal Virupakshappa is responsible for the development of the deep learning algorithm for ultrasonic NDT. Erdal Oruklu has contributed to hardware & software design, algorithm development, analysis and verification. The first draft of the manuscript was written by Yu Yuan and all authors read and approved the final manuscript.
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Yuan, Y., Virupakshappa, K. & Oruklu, E. Accelerating a Meta Learning Model for Ultrasonic Non-Destructive Testing Applications Using Model Compression and FPGA Hardware. J Sign Process Syst 96, 15–29 (2024). https://doi.org/10.1007/s11265-023-01901-8
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DOI: https://doi.org/10.1007/s11265-023-01901-8