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Numerical analysis of hardware architecture for header compression and packet aggregation on wireless networks

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Abstract

This paper proposes a numerical analysis model to predict the processing delay of a hardware architecture for robust header compression and packet aggregation on wireless mesh networks. The analysis model is composed of a series of queue systems such as G/M/1, M [K]/M/1, M/M/1, and M/M/∞ that are one-to-one mapped into the constructed hardware components to characterize the concurrent operations and interactional relationship between encoding and decoding paths. Based on the co-simulation method which integrates NS-2 and SystemC, we show the analysis model properly approximates the processing delay of the hardware architecture. Additionally, the variation of processing delay occurring when a part of hardware components are differently configured is suitably characterized by the proposed model, and the overall mesh network behaviors is predicted by applying the numerical results into NS-2 simulations.

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Authors and Affiliations

  1. Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, Stony Brook University-SUNY, Stony Brook, NY, 11794-2350, USA

    Sangkil Jung & Sangjin Hong

Authors
  1. Sangkil Jung
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  2. Sangjin Hong
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Correspondence to Sangkil Jung.

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Jung, S., Hong, S. Numerical analysis of hardware architecture for header compression and packet aggregation on wireless networks. Wireless Netw 16, 1477–1491 (2010). https://doi.org/10.1007/s11276-009-0215-9

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  • DOI: https://doi.org/10.1007/s11276-009-0215-9

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