Abstract
This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.
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This work was supported by University of Ulsan, School of Excellence in Electrical Engineering in 2013.
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Furhad, H., Haque, M.A., Kim, CH. et al. An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture. Wireless Pers Commun 73, 1403–1419 (2013). https://doi.org/10.1007/s11277-013-1257-y
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DOI: https://doi.org/10.1007/s11277-013-1257-y