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An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

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Abstract

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.

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References

  1. Bakhouya, M., Suboh, S., Gaber, J., El-Ghazawi, T., & Niar, S. (2011). Performance evaluation and design tradeoffs of on-chip interconnect architectures. Journal of Simulation Modelling Practice and Theory, 19(6), 1496–1505.

    Article  Google Scholar 

  2. Grecu, C., Pande, P. P., Ivanov, A., & Saleh, R. (2004). Structured interconnect architecture: A solution for the non-scalability of bus-based SoCs. In 14th International Symposium of ACM Great Lakes. doi:10.1145/988952.988999.

  3. Zhonghai, L. (2007). Design and analysis of on-chip communication for network-on-chip platforms. Ph.D. dissertation, Royal Institute of Technology (KTH). http://kth.diva-portal.org/smash/record.jsf?pid=diva2:11666.

  4. Suboh, S., Bakhouya, M., Gaber, J., & El-Ghazawi, T. (2008). An interconnection architecture for network-on-chip systems. Journal of Telecommunication Systems, 37, 137–144. doi:10.1007/s11235-008-9077-1.

    Article  Google Scholar 

  5. Shtykh, R., & Jin, Q. (2011). A human-centric integrated approach to web information search and sharing. Journal of Human-centric Computing and Information Sciences. doi:10.1186/2192-1962-1-2.

  6. Sabbaghi, N. R., Modarressi, M., & Sarbazi-Azad, H. (2012). The 2D digraph-based NoCs: Attractive alternatives to the 2D mesh NoCs. Journal of Supercomputing, 59(1), 1–21.

    Article  Google Scholar 

  7. Geer, D. (2009). Networks on processors improve on-chip communications. IEEE Transactions on Computing, 42(3), 17–20.

    MathSciNet  Google Scholar 

  8. Anant, B., & Azad, N. (2011). Interconnect network analysis of many-core chips. IEEE Transactions on Electron Devices, 58(9), 2831–2837.

    Article  Google Scholar 

  9. Qiying, W., Tingting, Q., & Satoshi, F. (2011). A two-level caching protocol for hierarchical peer-to-peer file sharing systems. Journal of Convergence, 2(1), 11–16.

    Google Scholar 

  10. Neil, Y., & Stephen, Y. F. (2012). An integrated approach for internet resources mining and searching. Journal of Convergence, 3(2), 37–44.

    Google Scholar 

  11. Kumar, S., Jantsch, A., Soinien, J. P., Forsell, M., Millberg, M., Berg, J., Tiensyrj, K., & Hemani, A. (2002). A network-on-chip architecture and design methodology. In IEEE international symposium on VLSI (pp. 117–124).

  12. Guerrier, P., & Greiner, A. (2000). A generic architecture for on-chip packet-switched interconnections. In Automation and test in Europe: IEEE international conference on design, (pp. 250–256).

  13. Dally, W. J., & Towles, B. (2001). Route packets, not wires:on-chip interconnection networks. In IEEE International conference on design automation (pp. 683–689).

  14. Karim, F., Nguyen, A., & Dey, S. (2002). An interconnection architecture for networking systems on chip. IEEE Transactions on Microprocessors, 22(5), 36–45.

    Google Scholar 

  15. Seifi, M. R., & Eshghi, M. (2012). Clustered NoC, A suitable design for group communications in network-on-chip. Journal of Computer and Electrical Engineering, 38(1), 82–95.

    Article  Google Scholar 

  16. Furhad, H., & Kim, J. M. (2012). An enhanced clustered mesh topology for network-on-chip architecture. In International conference on advanced information technology and sensor application, 20.

  17. El, M. (2011). Networks-on-chips: Modeling, analysis and design methodologies. Ph.D dissertation, University of Victoria. http://hdl.handle.net/1828/3633.

  18. Banarjee, A. (2010). Communication flows in power-efficient network-on-chips. Technical Report, Computer Laboratory, University of Cambridge. http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-786.pdf.

  19. Bolotin, E., Cidon, I., Ginosar, R., & Kolodny, A. (2004). Cost Considerations in network-on-chip. Integration—The VLSI Journal, 38(1), 19–42.

    Article  Google Scholar 

  20. Ogras, U. Y., & Marculescu, R. (2005). Application-specific network-on-chip architecture customization via long-range link insertion. In IEEE/ACM International conference on computer aided design (pp. 246–253).

  21. Dally, W. J. (1991). Express cubes: Improving the performance of K-ary N-cube interconnection networks. IEEE Transactions on Computing, 40(9), 1016–1023.

    Article  Google Scholar 

  22. Feero, S. B., & Pande, P. P. (2009). Networks-on-chip in a three-dimensional environment: A performance evaluation. IEEE Transactions on Computing, 58(1), 32–45.

    Article  MathSciNet  Google Scholar 

  23. Shen, Z. (1998). Average diameter of network structures and its estimation. in ACM International symposium on applied, computing (pp. 593–597).

  24. Xu, Y., Zhou, J., & Liu, S. (2011). Research and analysis of routing algorithms for NoC. IEEE International Conference on Computer Research and Development, 2, 98–102.

    Google Scholar 

  25. Mubeen, S. (2009). Evaluation of source routing for mesh topology network-on-chip platforms. M.Sc. dissertation, Jonkoping Institute of Technology. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-9591.

  26. Lu, Z., Thid, R., Millberg, M., Nilsson, E. & Jantsch, A. (2005). NNSE: Nostrum network-on-chip simulation environment. In International conference on Swedish system-on-chip conference (pp. 18–19).

  27. Fazzino, F., Palesi, M. & Patti, D. (2006). Noxim: Network-on-chip simulator. http://noxim.sourceforge.net.

  28. Hossain, H., Ahmed, M., Nayeem, A.A., Islam, T.Z. & Akbar, M. (2007). Gpnocsim-A general purpose simulator for network-on-chip. In IEEE international conference on information and communication technology (pp. 54–57).

  29. Suboh, S., Bakhouya, M., Lopez-Buedo, S. & El-Ghazawi, T. (2008). Simulation-based approach for evaluating on-chip interconnect architectures. In IEEE international conference on programmable logic, (pp. 75–80).

  30. Pande, P. P., Grecu, C., Jones, M., Ivanov, A., & Saleh, R. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Transactions on Computers, 54(8), 1025–1040.

    Article  Google Scholar 

  31. Tobias, B. & Shankar, M. (2006). A survey of research and practices of network-on-chip. ACM Computing Surveys. doi:10.1145/1132952.1132953.

  32. Gehlot, P. & Chouhan, S. S. (2009). Performance evaluation of network-on-chip architectures. In IEEE international conference on emerging trends in electronic and photonic devices and systems (pp. 124–127).

  33. Buddha, S., & Daya, K. L. (2012). A novel energy-aware cluster head selection based on particle swarm optimization for wireless sensor networks. Journal of Human-centric Computing and Information Sciences. doi:10.1186/2192-1962-2-13.

  34. Pande, P. P., Grecu, C., Ivanov, A. & Saleh, R. (2003). Design of a switch for network-on-chip applications. InInternational symposium circuits and systems (pp. 217–220).

  35. Xinan, Z. (2009). Performance Evaluation of network-on-chip interconnect architectures. M.Sc. dissertation, University of Nevada, Las Vegas. http://digitalscholarship.unlv.edu/cgi/viewcontent.cgi?article=1077&context=thesesdissertations.

  36. Kahng, A. B., & Li, Bin. (2012). ORION 2.0: A power-area simulator for interconnection networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 191–196.

    Article  Google Scholar 

  37. Benini, L. & Micheli, G. D. (2001). Powering networks on chips: Energy-efficient and reliable interconnect design for SoCs. In Proceedings of 14th ISSI system, synthesis (pp. 33–38).

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Acknowledgments

This work was supported by University of Ulsan, School of Excellence in Electrical Engineering in 2013.

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Authors and Affiliations

  1. School of Electrical Engineering, University of Ulsan, Daehak-Ro Mugeo-Dong, Nam-Gu, Ulsan, 680-749, South Korea

    Hasan Furhad, Mohammad A. Haque & Jong-Myon Kim

  2. School of Electronics and Computer Engineering, Chonnam National University, Kwangju, 500-757, South Korea

    Cheol-Hong Kim

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  1. Hasan Furhad
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  2. Mohammad A. Haque
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  4. Jong-Myon Kim
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Correspondence to Jong-Myon Kim.

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Furhad, H., Haque, M.A., Kim, CH. et al. An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture. Wireless Pers Commun 73, 1403–1419 (2013). https://doi.org/10.1007/s11277-013-1257-y

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