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Parametric Analysis to Reduce Phase Noise of Frequency Synthesizers for Wireless Communication System

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Abstract

The aim of this paper is analysis and presenting a technique to reduce phase noise of frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of phase noise in phase locked loop based frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for phase noise in frequency synthesizer. The simulation results show the performance of the frequency synthesizer for the High Speed communication system.

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References

  1. Goldberg, B. G. (1999). Digital frequency synthesis demystified, 3rd edition. LLH Technology Publishing.

  2. Best, R. E. (2003). Phase-locked loops: Design, simulation & applications, 4th edition. McGraw-Hill Professional Engineering.

  3. Singh, G., & Sharma, S. (2012). Analysis and reduction of phase noise in frequency synthesizers for wireless communication system. AMIS, 7(1), 29–34.

    MathSciNet  Google Scholar 

  4. Rhee, W., Ainspan, H., Friedman, D., Rasmus, T., Garvin, S., & Cranford, C. (2008). A continuously tunable LC-VCO PLL with bandwidth linearization techniques for PCI express Gen2 applications. Journal of Semiconductor Technology and Science, 8(3), 200–209.

    Article  Google Scholar 

  5. Ayranci, E., Christensen, K., & Andreani, P. (2012). Enhancement of VCO linearity and phase noise by implementing frequency locked loop. In IEEE EUROCON 2007 the international conference on “computer as a tool”, Warsaw, pp. 2593–2599.

  6. Altman, E., Avrachenkov, K., & Garnaev, A. (2011). Jamming in wireless network under uncertainty. Mobile Networks and Applications, 16, 246–254.

    Article  Google Scholar 

  7. Holma, H., & Toskala, A. (2004). A WCDMA for UMTS, radio access for third generation mobile communication, 3rd edition.

  8. Rhee, W., Song, B. S., & Ali, A. (2000). A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order modulator. IEEE Journal of Solid-State Circuits, 35(10), 45–48.

    Article  Google Scholar 

  9. Banerjee, D. (2008). PLL performance, simulation and design, handbook, 3rd edition.

  10. Staszewski, R. B., & Balsara, P. T. (2005). Phase-domain all-digital phase-locked loop. IEEE Transactions on Circuits and Systems-II: Express Briefs, 52(3), 239–244.

    Article  Google Scholar 

  11. Perrott, M. H., Trott, M. D., & Sodini, C. G. (2002). A modeling approach for sigma-delta fractional-N frequency synthesizers allowing straightforward noise analysis. IEEE Journal Solid-State Circuits, 37(8), 1028–1038.

    Article  Google Scholar 

  12. Hill, M. T., & Cantoni, A. (2000). A digital implementation of a frequency steered phase locked loop. IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications, 47(6), 818–824.

    Article  Google Scholar 

  13. Telba, A., Noras, J. M., Abou El Ela, M., & AI Mashaq, B. (2004). Simulation technique for noise and timing Jitter in phase locked loop, ICM 2004 proceedings. In The 16th IEEE international conference on transactions on microelectronics, pp. 501–504.

  14. Scheiblhofer, S., Schuster, S., & Stelzer, A. (2006). Signal model and linearization for nonlinear chirps in FMCW radar SAW-ID tag request. IEEE Transactions on Microwave Theory and Techniques, 54(4), 1477–1483.

    Article  Google Scholar 

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Correspondence to Govind Singh Patel.

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Patel, G.S., Sharma, S. Parametric Analysis to Reduce Phase Noise of Frequency Synthesizers for Wireless Communication System. Wireless Pers Commun 75, 1295–1306 (2014). https://doi.org/10.1007/s11277-013-1424-1

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  • DOI: https://doi.org/10.1007/s11277-013-1424-1

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