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Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA

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Abstract

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

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References

  1. Hsiao, S. W. (2012). An area-efficient 3.5 GHz fractional-N frequency synthesizer with capacitor multiplier in millimeter-wave gigabit wireless communication. In IEEE 13th annual conference in wireless and microwave technology (WAMICON) (pp. 1–5).

  2. Kohtani, M. (2015) Multiplier circuit and wireless communication apparatus using the same. U.S. Patent Application 14/101,803.

  3. Brown, S. J., Estrada, A. X., Bourk, T. R., Norsworthy, S. R., Murphy, P. J., Hull, C. D., et al. (2002). U.S. Patent No. 6,366,622. Washington, DC: U.S. Patent and Trademark Office.

  4. Kayal, D., Mostafa, P., Dandapat, A., & Sarkar, C. K. (2013). Design of high performance 8 bit multiplier using vedic multiplication algorithm with McCMOS technique. Journal of Signal Processing Systems, 76(1), 1–9.

    Article  Google Scholar 

  5. Blaauw, D., Martin, S., Mudge, T., & Flaunter, K. (2002). Leakage current reduction in VLSI systems. Journal of Circuits, Systems, and Computers, 11(06), 621–635.

    Article  Google Scholar 

  6. Pandey, B., Goswami, K. (2014). LVCMOS based thermal aware energy efficient vedic multiplier design on FPGA. In IEEE 6th international conference on computational intelligence and communication networks (CICN).

  7. Pandey, B., Goswami, K. (2014). Low voltage digitally controlled impedance based energy efficient vedic multiplier design on 28 nm FPGA. In IEEE 6th international conference on computational intelligence and communication networks (CICN).

  8. Pradhan, M., Panda, R., & Sahu, S. K. (2011). Speed comparison of 16 × 16 vedic multipliers. International Journal of Computer Applications, 21(6), 0975–8887.

    Article  Google Scholar 

  9. Rudagi, J.M., Amble, V., Munavalli, Patil, R., Sajjan,V. (2011). Design and implementation of efficient multiplier using vedic mathematics. In International conference on advances in recent technologies in communication and computing (ARTCom) (pp. 162–166).

  10. Kunchigi, V., Kulkarni, L., Kulkarni, S. (2009). High speed and area efficient vedic multiplier. In IEEE international conference on devices, circuits and systems (ICDCS), Coimbatore, (pp. 360–364).

  11. Pushpangadan, R., Sukumaran, V., et al. (2009). High speed vedic multiplier for digital signal processors. IETE Journal of Research, 55(6), 282–286.

    Article  Google Scholar 

  12. Thapliyal, H., & Arabnia, H. R. (2004). A time-area-power efficient multiplier and square architecture based on ancient indian vedic mathematics. Athens, USA: Department of Computer Science, The University of Georgia, 415 Graduate Studies Research Center.

    Google Scholar 

  13. Virtex-6 SelectIO Resources User Guide www.xilinx.com. UG361 (v1.5) March 21, 2014.

  14. Kumar, P., Radhika, U.C.S. (2013). FPGA Implementation of high speed 8-bit vedic multiplier using barrel shifter. In International conference on energy efficient technologies for sustainability (ICEETS) (pp. 14–17).

  15. Rajput, N., Jindal, A., Saroha, S., Kumar, R., & Sharma, G. (2013). A novel and high performance implementation of 8 × 8 multiplier based on vedic mathematics using 90 nm hybrid PTL/CMOS logic. International Journal of Computer Applications, 69(27), 0975–8887.

    Article  Google Scholar 

  16. Itawadiya, A.K., Mahle, R., Patel, V., Kumar, D. (2013). Design a DSP operations using vedic mathematics. In IEEE international conference on communication and signal processing (ICCSP) (pp. 897–902).

  17. Saligram, R., Rakshith, T.R. (2013). Optimized reversible vedic multipliers for high speed low power operations. In IEEE conference on information and communication technologies (ICT) (pp. 809–814).

  18. Kumar, T., Pandey, B., Das, T., & Chowdhry, B. S. (2014). Mobile DDR IO standard based high performance energy efficient portable ALU design on FPGA. Wireless Personal Communications, 76(3), 569–578.

    Article  Google Scholar 

  19. Pandey, B., et al. (2014). LVTTL based energy efficient watermark generator design and implementation on FPGA. In IEEE international conference on ICT convergence 2014, Busan, Korea, 10.1109/ICTC.2014.6983240.

  20. Kumar, T., Pandey, B., Das, T. (2013). LVCMOS I/O standard and drive strength based green design on ultra scale FPGA. In IEEE international conference on green computing, communication and conservation of energy.

  21. Singh, P., Pandey, B., Kumar, T., Das, T. (2014). I/O standard based power optimized processor register design on ultra scale FPGA. In IEEE international conference on computing for sustainable global development (INDIACOM).

  22. Kumar, T., Pandey, B., Musavi, S.H.A., Zaman, N. (2015). CTHS based energy efficient thermal aware image ALU design on FPGA. Springer Wireless Personal Communications, An International Journal, ISSN:0929-6212(print), ISSN:1572-834X(electronic).

  23. Musavi, S.H.A., Chowdhry, B.S., Kumar, T., Pandey, B., Kumar, W. (2015). IoTs enable active contour modeling based energy efficient and thermal aware object tracking on FPGA. Springer Wireless Personal Communications, ISSN:1572-834X (electronic), SCI Indexed, 82(3):1–15, http://link.springer.com/article/10.1007/s11277-015-2753-z.

  24. Dabbas, S., Pandey, B., Kumar, T., Das, T. (2014). Design of power optimized memory circuit using high speed transceiver logic IO standard on 28 nm field programmable gate array. In IEEE international conference on reliability optimization and information technology (ICROIT).

  25. Kumar, T., Pandey, B., Das, T., Rahman, M.A. (2013). SSTL based green image ALU design on different FPGA. In IEEE international conference on green computing, communication and conservation of energy (ICGCE).

  26. Kumar, T., Pandey, B., Das, T., Minver, M.H. (2013). LVDCI I/O standard based green image ALU design on ultra scale FPGA. In IEEE 8th international conference on industrial and information systems (ICIIS) (pp. 283–288).

  27. Pandey, B., Kumar, T., Das, T., & Kumar, J. (2014). Thermal mechanics based energy efficient FIR filter for digital signal processing. Applied Mechanics and Materials (AMM) Journal, 612, 65–70.

  28. Huang, W., Stan, M. R., Skadron, K., Sankaranarayanan, K., Ghosh, S., & Velusam, S. (2004). Compact thermal modeling for temperature-aware design. In Proceedings of the 41st annual design automation conference (ACM) (pp. 878–883).

  29. Chowdhry, B.S., Pandey, B., Kumar, T., Das, T., Thakur, S. (2014). Frequency, voltage and temperature sensor design for fire detection in VLSI circuit on FPGA. Springer Communications in Computer and Information Science, (Vol. 414, pp. 121–133), ISSN: 1865-0929. http://link.springer.com/chapter/10.1007/978-3-319-10987-9_12.

  30. Ogras, U. Y., Hu, J., & Marculescu, R. (2005). Key research problems in NoC design: A holistic perspective. In Proceedings of the 3rd IEEE/ACM/IFIP international conference of Hardware/software codesign and system synthesis (pp. 69–74).

  31. Uddin, A., Banshal, S., Rahman, MA, Das, T., Kumar, T., Pandey, B. (2014). Thermal aware energy efficient bengali unicode reader in text analysis. In IEEE international conference on reliability optimization and information technology (ICROIT).

  32. Hung, W. L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, T., & Irwin, M. J. (2005). In Sixth international symposium on thermal-aware floor planning using genetic algorithms in quality of electronic design (pp. 634–639).

  33. Kumar, T., Das, T., Pandey, B., Hussain, D.M.A. (2014). IO standard based thermal/energy efficient green communication for wi-fi protected access on FPGA. In IEEE 6th international congress on ultra-modern telecommunications and control systems and workshops, St. Petersburg, Russia. 10.1109/ICUMT.2014.7002085.

  34. Sankaranarayanan, K., Velusamy, S., Stan, M., & Skadron, K. (2005). A case for thermal-aware floor planning at the micro architectural level. Journal of Instruction-Level Parallelism, 7(1), 8–16.

    Google Scholar 

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Authors and Affiliations

  1. ECE Department, Chitkara University, Chandigarh, India

    Kavita Goswami & Bishwajeet Pandey

  2. Indus University, Karachi, Pakistan

    Tanesh Kumar

  3. Aalborg University, Esbjerg, Denmark

    D. M. Akbar Hussain

Authors
  1. Kavita Goswami
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  2. Bishwajeet Pandey
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  3. Tanesh Kumar
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  4. D. M. Akbar Hussain
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Correspondence to Tanesh Kumar.

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Goswami, K., Pandey, B., Kumar, T. et al. Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA. Wireless Pers Commun 96, 3139–3158 (2017). https://doi.org/10.1007/s11277-017-4345-6

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  • DOI: https://doi.org/10.1007/s11277-017-4345-6

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