Abstract
Arithmetic Logic Units (ALUs) are very important components of the processor, which performs various arithmetic and logical operations such as multiplication, division, addition, subtraction, cubing, squaring, etc. Of these all operations, multiplication is most elementary and most frequently used operation in the ALUs. The operation of multiplication also forms the basis of many other complex arithmetic operations such as cubing, squaring, convolution, etc. This paper presents the modified novel multi-precision binary multiplier architecture to achieve a reduced latency/delay and area/hardware utilization along with existing implementations of binary multiplication. This system will function as second stage of the of a novel multi-precision binary multiplier system. The system was implemented using Xilinx 14.2 ISE and simulated with ISIM which was available from Xilinx 14.2 ISE. The results of simulation indicate that the latency of the proposed novel binary multiplier systems (8-bit, 16-bit and 24-bit) with significantly shorter than existing implementations.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Perry, D. (1998). VHDL (3rd ed.). New York: McGraw-Hill.
Hennessey, J., & Patterson, D. (2003). Computer architecture. A quantitative approach (3rd ed.). San Francisco: Morgan Kaufmann Publishers.
Michael, D. C., Zhang, Y. Q., & Li, Q. (2005). Advanced digital with the verilog HDL etc translating. Beijing: Publishing House of Electronics Industry.
Kodali, R. K., Boppana, L., Yenamachintala, S. S. (2015). FPGA implementation of vedic floating point multiplier. In: IEEE international conference on signal processing, informatics, communication and energy systems (SPICES) (pp. 1–4). https://doi.org/10.1109/SPICES.2015.7091534.
Abraham, S., Kaur, S., & Singh, S. (2015). Study of various high speed multipliers. In international conference on computer communication and informatics (ICCCI) (pp. 1–5). https://doi.org/10.1109/ICCCI.2015.7218139.
Vyas, K., Jain, G., Maurya, V. K. & Mehra, A. (2015). Analysis of an efficient partial product reduction technique. In International conference on green computing and internet of things (ICGCIoT) (pp 1–6). https://doi.org/10.1109/ICGCIoT.2015.7380417.
Anitha, P., & Ramanathan, P. (2014). A new hybrid multiplie using Dadda and Wallace method. In International conference on electronics and communication systems (ICECS) (pp 1–4). https://doi.org/10.1109/ECS.2014.6892623.
Chopade, S. S., & Mehta, R. (2015). Performance analysis of vedic multiplication technique using FPGA. In IEEE Bombay section symposium (IBSS) (pp. 1–6). https://doi.org/10.1109/IBSS.2015.7456657.
Bisoyi, A., Baral, M., & Senapati, M. K. (2014). Comparison of a 32-bit vedic multiplier with a conventional binary multiplier. In International conference on advanced communication control and computing technologies (ICACCCT) (pp 1757–1760) https://doi.org/10.1109/ICACCCT.2014.7019410.
Mhaidat, K. M., & Hamzah, A. Y. (2014). A new efficient reduction scheme to implement tree multipliers on FPGAs. In 9th international design and test symposium (pp 180–184) https://doi.org/10.1109/IDT.2014.7038609.
Bathija, R. K., Meena, R. S., Sarkar, S., & Sahu, R. (2012). Low power high speed 16 × 16 bit multiplier using vedic mathematics (0975–8887). International Journal of Computer Applications., 59(6), 41–44.
Rao, M. J., & Dubey, S. (2012). A high speed and area efficient booth recoded Wallace tree multiplier for fast arithmetic circuits. In Asia Pacific conference on postgraduate research in microelectronics & electronics (PRIMEASIA) (pp. 220–223).
Jain, A., Dash, B., Panda, A. K., & Suresh, M. (2012). FPGA design of a fast 32-bit floating point multiplier unit. In International conference on devices, circuits and systems (ICDCS) (pp. 545–547).
Arish, S., & Sharma, R. K. (2015). An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm. In Global conference on communication technologies (GCCT) (pp 192–196). https://doi.org/10.1109/GCCT.2015.7342650.
Gokhale, G. R., & Bahirgonde, P. D. (2015). Design of vedic-multiplier using area-efficient carry select adder. In International conference on advances in computing, communications and informatics (ICACCI) (pp. 576–581). https://doi.org/10.1109/ICACCI.2015.7275671.
Sharma, R., Kaur, M., & Singh, G. (2015). Design and FPGA implementation of optimized 32-Bit vedic multiplier and square architectures. In International conference on industrial instrumentation and control (ICIC) ( pp. 960–964) College of Engineering Pune, India. May 28–30. https://doi.org/10.1109/IIC.2015.7150883.
Rao, Y. S., Kamaraju, M., & Ramanjaneyulu, D. V. S. (2015). An FPGA implementation of high speed and area efficient double-precision floating point multiplier using Urdhva Tiryagbhyam technique. In Conference on power, control, communication and computational technologies for sustainable growth (PCCCTSG) (pp. 271–276). https://doi.org/10.1109/PCCCTSG.2015.7503923.
Marcus, G., & Tomar, G. S. (2015) Hardware design procedure: principles and practices. In Fifth international conference on communication systems and network technologies (pp. 834–838).
Sateesh, B. V., & Chacko, S. C. (2014). A high speed and area efficient wallace tree multiplier with booth recoded technique. International Journal of Computer Science and Mobile Computing., 3(3), 510–518.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Tomar, G.S., George, M.L. Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization. Wireless Pers Commun 98, 3549–3561 (2018). https://doi.org/10.1007/s11277-017-5028-z
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11277-017-5028-z