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Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic

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Abstract

The finite impulse response (FIR) digital filters are commonly used in many digital signal processing systems. For higher order filters the implementation of reconfigurable random access memory based FIR filter becomes costly and the speed is reduced. This research paper presents an efficient distributed arithmetic (DA) based approach for reduced area and low power implementation of the FIR filters whose filter coefficients are dynamic in nature. Due to the complexity in implementation of higher order filters, a portion of bit serial based computation in the look up table (LUT) is used. However the shared LUTs are used instead of RAM based LUTs, Shared LUTs involves the concept of LUT partitioning where the coefficients are split into vectors of smaller bit lengths which reduce the depth of the LUT. The possible partial DA results for these vectors are stored in register banks that are shared between multiple DA units. Since the register banks are shared, the area is effectively reduced. Hence an application specific integrated circuits implementation is used. When compared to the existing 256 tap FIR filter, the area has been reduced by 62.16% for vector bit length (M), M = 2 and by 75.84% for M = 4 and the power consumption has been reduced by 42.67% for M = 2 and by 64.02% for M = 4.

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Authors and Affiliations

  1. Department of ECE, SRM Institute of Science and Technology, Chennai, India

    E. Chitra & S. Malarvizhi

  2. VIT, Chennai, India

    T. Vigneswaran

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  1. E. Chitra
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  2. T. Vigneswaran
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  3. S. Malarvizhi
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Correspondence to E. Chitra.

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Chitra, E., Vigneswaran, T. & Malarvizhi, S. Analysis and Implementation of High Performance Reconfigurable Finite Impulse Response Filter Using Distributed Arithmetic. Wireless Pers Commun 102, 3413–3425 (2018). https://doi.org/10.1007/s11277-018-5375-4

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