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Using DRAM Buffer to Reduce Persistence and Consistence Overheads of Persistent Memory

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Abstract

Persistent memory has the potential to become universal storage for memory and storage uses. Unfortunately, our system architecture is good fit for two-level storage model with DRAM and storage. It incurs two of important performance overheads. First is higher latency and degrading concurrent performance due to the requirements of persistence and consistency of persistent memory. Another is to abstract in-memory objects into file although these in-memory objects are already persistent, or to load data objects from files even they are in memory. We propose a hybrid storage model with a persistent objects management system to manage in-persistent memory data sets. Persistent memory plays dual roles of memory and storage, CPU directly access in-persistent memory data sets, and these data sets are not required serializing or de-serializing into files, managed by persistent object management system. To lower overheads introduced by high latency and consistence of persistent memory, DRAM is used as buffer, shifting persistency and consistence from each application to our management process, named persistent memory server engine. The experiment results show that our prototype can benefit file-intensive, data-intensive applications and relational databases, providing 15–63% better performance than persistent heap and persistent memory file systems using direct access method.

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Acknowledgements

The work was partly supported by National Basic Research 973 Program of China under Grant No. 2011CB302301; NSFC No. 61025008, 61173043, and 61232004; 863 Project 2013AA013203; Electronic Development fund of Information Industry Ministry. The work was also supported by Key Laboratory of Information Storage System, Ministry of Education, China. The authors are also grateful to anonymous reviews for their feedback.

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Correspondence to Yuchuan Tian.

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Tian, Y., Wang, F. Using DRAM Buffer to Reduce Persistence and Consistence Overheads of Persistent Memory. Wireless Pers Commun 102, 3879–3896 (2018). https://doi.org/10.1007/s11277-018-5418-x

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