Abstract
Static or leakage power is the dominating component of total power dissipation in deep nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm to 54% at 65 nm technology due to continued device and voltage scaling. Static random access memory (SRAM) is a type of RAM in which data is not written permanently and it does not need to be refreshed periodically. Different techniques have been applied to SRAM cell to reduce leakage power without affecting its performance. A novel 10T SRAM architecture is proposed in this paper which operates in three modes (active, park, standby or hold). The main objective of the proposed architecture is to provide better stability and reduced delay in active mode, reduced leakage current in standby mode and retaining the logic state in park mode. Design metrics such as static and dynamic power, delay, power delay product, energy, energy delay product, rise and fall time, slew rate and static noise margin are taken into account. All the circuits were designed using SYNOPSYS EDA tool and simulated in 30 nm technology. Simulation results shows that the proposed SRAM is much better than conventional and other SRAM cells designed using hybrid techniques.
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References
Singh, S., & Akashe, S. (2017). Low power consuming 1 KB (32 3 32) memory array using compact 7T SRAM cell. Wireless Personal Communications, 96, 1099–1109.
Nayak, D., & Mahapatra, K. (2017). Current starving the SRAM cell: A strategy to improve cell stability and power. Circuits Syst Signal Process, 36, 3047–3070.
Upadhyay, P., & Kar, R. (2015). A design of low swing and multithreshold voltage based low power 12T SRAM cell. Integration the VLSI Journal, 45, 108–121.
Akashe, S., & Sharma, S. (2013). Leakage current reduction technique for 7T SRAM cell in 45 nm technology. Wireless Personal Communications, 71, 123–136.
Islam, A., & Hasan, M. (2012). Leakage characterization of 10T SRAM cell. IEEE Transactions on Electron Device, 59, 631–638.
Pasendiand, G., & Fakharaie, S. M. (2014). An 8T low voltage and low leakage half selection disturb free SRAM using Bulk-CMOS and FINFET. IEEE Transactions on Electron Devices, 61, 2357–2363.
Lorenzo, R., & Chaudhury, S. (2017). A novel SRAM cell design with a body-bias controller circuit for low leakage, high speed and improved stability. Wireless Personal Communications, 94, 3513–3529.
Kim, J., & Mazumder, P. (2017). A robust 12T SRAM cell with improved write marign for ultra-low power applications in 40 nm CMOS. Integration the VLSI Journal, 57, 1–10.
Kim, J., & Chang, J. (2015). Supply voltage decision methodology to minimize standby power under radiation environment. IEEE Transactions on Nuclear Science, 62, 1349–1356.
Kursan, V., & Zhu, H. (2014). Novel low leakage and high speed triple threshold voltage buffer with skewed inputs and outputs. IEEE Transactions on Circuits and Systems, 61, 2013–2021.
Lorenzo, R., & Chaudhury, S. (2017). Dynamic threshold sleep transistor technquie for high speed and low leakage in CMOS circuits. Circuits System and Signal Processing, 36, 2654–2671.
Prasad, G., & Anand, A. (2015). Statistical analysis of low-power SRAM cell structure. Analog Integrated Circuits and Signal Processing, 82, 349–358.
Chen, Y. G., Shi, Y., & Geng, H. (2014). Multibit retention register for power gated design. IEEE Transactions on Computer Aided Design, 33, 507–518.
Lorenzo, R., & Chaudhury, S. (2017). A novel 9T SRAM architecture for low leakage and high performance. Analog Integrated Circuits and Signal Processing, 92, 315–325.
Jiao, H., & Kursun, V. (2016). Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. Integration the VLSI Journal, 53, 68–79.
Nakhate, S., & Yadav, A. S. (2015). Low standby leakage 12T SRAM cell characterization. International Journal of Electronics, 103, 1446–1459.
Lorenzo, R., & Chaudhury, S. (2016). Review of circuit level leakage minimization techniques in CMOS VLSI circuits. IETE Technical Review, 34, 165–187.
Tiwari, N., & Atre, P. (2017). Highly robust asymmetrical 9T SRAM with trimode MTCMOS technique. Microsystem Technologies, 10, 1007–1015.
Lorenzo, R., & Chaudhury, S. (2017). LCNT- an approach to reduce leakage power in CMOS integrated circuits. Microsystem Technologies, 23, 4245–4253.
Peri, S., & Lanuzza, M. (2014). Gate level body biasing technique for high speed sub-threshold CMOS logic gates. International Journal Circuit Theory Applications, 42, 65–70.
Torrens, G., & Alorda, B. (2014). Adaptive static and dynamic noise margin improvement in minimum sized 6T SRAM cells. Microelectronics Reliability, 11, 2613–2620.
Zhang, L., & Mao, L. (2012). Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process. Micro & Nano Letters, 7, 171–173.
Jiao, H., & Kursun, V. (2010). Trimode operation for noise reduction and data preservation in low leakage multi threshold CMOS circuits. In 18th International Conference on Very Large Scale Integration (VLSISOC), Madrid, Spain (pp. 258–290). https://doi.org/10.1007/978-3-642-28566-0_1.
Moghaddam, M., & Timarchi, S. (2016). An ultra low power 9T SRAM cell based on threshold voltage techniques. Circuits, Systems and Signal Processing, 35, 1437–1455.
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Gavaskar, K., Ragupathy, U.S. & Malini, V. Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories. Wireless Pers Commun 108, 2311–2339 (2019). https://doi.org/10.1007/s11277-019-06523-7
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DOI: https://doi.org/10.1007/s11277-019-06523-7