Abstract
Content Addressable Memory (CAM) is used in high speed searching applications and also in data compression. Recently in the network computing era, fast lookup tables are required for address resolution in network switches and routers such as LAN bridges/switches, ATM switches, and layer-3 switches. High search speed is obtained by parallel comparison. But power consumption is high in case of parallel comparison. In precomputation based CAM (PB-CAM) the comparison operation is divided into two stages to reduce the massive comparison operations in data searches. Precomputation is the way of comparing the extracted parameter from the input data in the first stage. The second stage comparison is done between the matched output of the first stage and the input data. In this paper, a Remainder Function parameter extractor is proposed as a precomputation technique to enhance the performance of low power PB-CAM. The experimental results obtained using 90 nm CMOS technology in the Cadence virtuoso show that the proposed approach achieves an average of 91% in power reduction.
Similar content being viewed by others
References
Pagiamtzis, K., & Sheikholeslami, A. (2006). Content-addressable memory (cam) circuits and architectures: A tutorial and survey. IEEE Journal of Solid-State Circuits,41, 712–727.
Chang, Y.-J., Member, I. E. E. E., & Liao, Y.-H. (2008). Hybrid-type CAM design for both power and performance efficiency. IEEE Transactions on Very Large Scale Integration Systems,116, 965–974.
Miyatake, H., Tanaka, M., & Mori, Y. (2001). A design for high-speed low-power cmos fully parallel content-addressable memory macros. IEEE Journal of Solid-State Circuits,36, 956–968.
Arsovski, I., & Sheikholeslami, A. (2003). A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. IEEE Journal of Solid-State Circuits,11, 1958–1966.
Cheng, K. H., Wei, C. H., & Jiang, S. Y. (2004). Static divided word matching line for low-power content addressable memory design. In Proceedings of international symposium on circuits and systems (pp. 629–632).
Chang, Yen-Jen, & Tung-Chi, Wu. (2015). Master-slave matchline design for low power content addressable memory. IEEE Transactions on Very Large Scale Integration Systems,23, 1740–1749.
Pagiamtzis, K., & Sheikholeslami, A. (2004). A low-power content-addressable memory(CAM) using pipelined hierarchical search scheme. IEEE Journal of Solid-State Circuits,39, 1512–1519.
Zukowski, C. A., & Wang, S. Y. (1997). Use of selective precharge for low-power content-addressable memories. In Proceedings of international symposium on circuits and systems (pp. 1788–1791).
Lin, C.-S., Chang, J.-C., & Liu, B.-D. (2003). A low-power precomputation-based fully parallel content-addressable memory. IEEE Journal of Solid-State Circuits,38, 654–662.
Ruan, S.-J., Wu, C.-Y., & Hsieh, J.-Y. (2008). Low power design of precomputation-based content addressable memory. IEEE Transactions on Very Large Scale Integration Systems,16, 331–335.
Hsieh, J.-Y., & Ruan, S.-J. (2008). Synthesis and design of parameter extractors for low power precomputation based content addressable memory using gate block selection algorithm. In IEEE Asia and South Pacific design automation conference.
Do, A. T., Chen, S. S., Kong, Z. H., & Yeo, K. S. (2011). A low-power CAM with efficient power and delay trade-off. In Proceedings of IEEE international symposium on circuits and systems (ISCAS) (pp. 2573–2576).
Do, A.-T., Chen, S., Kong, Z.-H., & Yeo, K. S. (2013). A high speed low power CAM with a parity bit and power-gated ML sensing. IEEE Transactions on Very Large Scale Integration Systems,21, 151–156.
Georgiev, D. (2013). Low power concept for content addressable memory (CAM) chip design. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering,2, 3165–3170.
Gupta, M., & Gupta, V. K. (2015). Design of content addressable memory (CAM) architecture. International Journal of Science and Research,4, 1870–1873.
Kameswaran, A., Nanthakumar, K., & Ruba, M. (2017). High performance pre-computation based self-controlled precharge-free content-addressable memory. Journal of Electronics and Communication Systems,2, 1–9.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Mythili, R., Kalpana, P. Comparative Analysis of Parameter Extractor for Low-Power Precomputation Based Content Addressable Memory. Wireless Pers Commun 111, 1313–1326 (2020). https://doi.org/10.1007/s11277-019-06916-8
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11277-019-06916-8