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Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

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Abstract

This work proposed the design of low power Si0.7Ge0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value ION/IOFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.

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  1. School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

    Suman Lata Tripathi & Govind Singh Patel

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  1. Suman Lata Tripathi
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  2. Govind Singh Patel
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Correspondence to Suman Lata Tripathi.

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Tripathi, S.L., Patel, G.S. Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology. Wireless Pers Commun 111, 2167–2176 (2020). https://doi.org/10.1007/s11277-019-06978-8

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