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Performance Analysis of CGOH, Parrallelized and Pipelined ALU for Low Power FPGA Implementations in IOT Framework

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Abstract

Nowadays, FPGAs has seen a rapid growth for the development of scalable 5G and Internet of Things (IoT) devices. Modern FPGAs play an important role to provide computational power to IoT devices in an IoT framework. The IoT devices consume more power during data processing and transmission. This creates the concern of developing low power techniques for FPGA based IoT nodes. The commercial tools like Xilinx and Vivado are nowadays automated their design flow with the options of low power techniques. This felicitates the designers to implement optimized low power designs for IoT applications. However, limited options are available in the design flow and there is a scope to incorporate more low power techniques options. Further, the impact of power reduction on area and delay parameters is missing in literature. Therefore, this paper extend the work of Gaurav et al. (GCWOT 1–5, 2020) and proposed three power minimization techniques, namely CGOH (fusion of clock gating and one hot coding), parallelism and pipelining for arithmetic and logical unit that leads to three different designs of ALU. These designs are coded in VHDL, synthesized using Xilinx Synthesis Tool (XST), and tested using Xpower Analyzer for power analysis. The performance analysis of the three different designs has been done on the basis of power, area and delay and compared with the normal design of the ALU (without any technique). The CGOH technique shows 9.5% reduction in power at 300 MHz frequency with 22% increase in area and 1.48% decrease in speed. The parallelism technique shows 35.68% reduction in power at 265 MHz frequency with 5.92% increase in area and 14.04% decrease in speed. The pipelining technique shows 31.92% reduction in power at 241 MHz frequency with 8.01% increase in area and 21.54% decrease in speed. The parallelized design of ALU has better operating frequency, less critical path delay and less power consumption although at the expense of a slight more area as compared to the pipelined design.

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Data Availability

Not applicable.

Code Availability

All the experiments have been performed using standard Xilinx ISE Tool.

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  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, A-10, Sector-62, Noida, Uttar Pradesh, India

    Gaurav Verma

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Verma, G. Performance Analysis of CGOH, Parrallelized and Pipelined ALU for Low Power FPGA Implementations in IOT Framework. Wireless Pers Commun 126, 3233–3251 (2022). https://doi.org/10.1007/s11277-022-09861-1

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