Skip to main content
SpringerLink
Log in

Performance Analysis of Enhanced AES-128 and Blowfish Algorithms Through Parallel-Pipelined-Memory Techniques

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

Currently, the advanced encryption standard (AES)-128 algorithm is deployed by the Institute of Electrical and Electronics Engineers standards, and it is widely used to secure wireless communication in various radio frequency bands. This paper proposes an enhanced Blowfish algorithm with better performance than the AES-128 as a potential security function to be implemented in mobile devices. A performance analysis based on Artix-7 field programmable gate array platform is conducted in terms of the design throughput, hardware utilisation and power consumption of the proposed AES-128 and Blowfish architectures, which are enhanced by using the parallel–pipelined–memory (P2M) techniques. These techniques contribute to the performance improvement of the P2M AES-128 and P2M Blowfish, with the proposed Blowfish achieving 50% better power throughput and 45.3% lower logic resources. Findings show that the P2M Blowfish not only secures mobile devices but can also reduce the design space and prolong battery lifetime for longer usage at a high data rate.

Graphical abstract

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

Data Availability

Not applicable.

Code availability

Not applicable.

References

  1. Niu, Y., Zhang, J., Wang, A., & Chen, C. (2019). An efficient collision power attack on AES encryption in edge computing. IEEE Access, 7, 18734–18748. https://doi.org/10.1109/ACCESS.2019.2896256

    Article  Google Scholar 

  2. Bhanot, R., & Hans, R. (2015). A review and comparative analysis of various encryption algorithms. International Journal of Security and its Applications, 9(4), 299–306. https://doi.org/10.14257/IJSIA.2015.9.4.27

    Article  Google Scholar 

  3. Guo, S., Zhao, X., Zhang, F., Wang, T., Shi, Z., Standaert, F. X., & Ma, C. (2014). Exploiting the incomplete diffusion feature: A specialized analytical side-channel attack against the AES and its application to microcontroller implementations. IEEE Transaction on Information Forensics and Security, 9(6), 999–1014.

    Article  Google Scholar 

  4. Schneier, B. (2009). Schneier on security: Another new AES attack. Retrieved 5 Sept 2016 from https://www.schneier.com/blog/archives/2009/07/another_new_aes.html

  5. CISCO. (2019). Securing the internet of things: A proposed framework. Retrieved 16 Jan 2019 from http://www.cisco.com/c/en/us/about/security-center/secure-iot-proposed-framework.html

  6. Tentu, A. N. (2020). A review on evolution of symmetric key block ciphers and their applications. IETE Journal of Education, 61(1), 34–46. https://doi.org/10.1080/09747338.2020.1769508

    Article  MathSciNet  Google Scholar 

  7. Abd Elminaam, D. S., Kader, H. M. A., & Hadhoud, M. M. (2010). Evaluating the performance of symmetric encryption algorithms. International Journal of Network Security, 10(3), 213–219.

    Google Scholar 

  8. Thakur, J., & Kumar, N. (2011). DES, AES and blowfish: symmetric key cryptography algorithms simulation based performance analysis. International Journal of Emerging Technology and Advanced Engineering, 1(2), 6–12.

    Google Scholar 

  9. Mandal, P. C. (2012). Superiority of blowfish algorithm. International Journal of Advanced Research in Computer Science and Software Engineering, 2(9), 196–201.

    Google Scholar 

  10. Prakash, A., Lam, S. K., Clarke, C. T., & Srikanthan, T. (2013). FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocessors and Microsystems, 37(2013), 259–269. https://doi.org/10.1016/j.micpro.2013.02.002

    Article  Google Scholar 

  11. Devi, A., Sharma, A., & Rangra, A. (2015). Performance analysis of symmetric key algorithms: DES, AES, and blowfish for image encryption and decryption. International Journal of Engineering and Computer Science, 4(6), 12646–12651.

    Google Scholar 

  12. Patil, P., Narayankar, P., Narayan, D.G., & Meena, S.M. (2016). A comprehensive evaluation of cryptographic algorithms: DES, 3DES, AES, RSA and Blowfish. In: Proceedings of the 2016 International Conference on Information Security & Privacy (ICISP2015), Procedia Computer Science, Elsevier, 78; pp. 617–624, Nagpur, India.

  13. Rajasekaravarma, S., & Joshna, S. (2016). Symmetric key algorithms: a comparative analysis. International Journal of Innovative Research in Computer and Communication Engineering, 4(9), 15772–15775.

    Google Scholar 

  14. Silva, N. B. F., Pigatto, D. F., Martins, P. S., & Branco, K. R. L. J. C. (2016). Case studies of performance evaluation of cryptographic algorithms for an embedded system and a general purpose computer. Journal of Network and Computer Applications, 20, 13–143. https://doi.org/10.1016/j.jnca.2015.10.007

    Article  Google Scholar 

  15. Sohal, M., & Sharma, S. (2018). BDNA-A DNA inspired symmetric key cryptographic technique to secure cloud computing. Journal of King Saud University, Computer and Information Sciences, 1–9, in press.

  16. Nazeh Abdul Wahid, M. N., Ali, A., Esparham, B., & Marwan, M. D. (2018). A comparison of cryptographic algorithms: DES, 3DES, AES, RSA and blowfish for guessing attacks prevention. Journal of Computer Science Applications and Information Technology, 3(2), 1–7.

    Google Scholar 

  17. Schneier, B., & Whiting, D. (1997). Fast software encryption: designing encryption for optimal speed on the Intel Pentium processor. In: Proceedings of 4th international workshop on fast software encryption. LNCS, pp. 242–259. Springer Verlag.

  18. Ghosh, S., & Karar, V. (2018). Blowfish hybridized weighted attribute-based encryption for secure and efficient data collaboration in cloud computing. Applied Sciences, 8(1119), 1–15. https://doi.org/10.3390/app8071119

    Article  Google Scholar 

  19. Fan, C. P., & Hwang, J. K. (2008). FPGA implementations of high throughput sequential and fully pipelined AES algorithm. International Journal of Electrical Engineering, 15(6), 447–455.

    Google Scholar 

  20. Prasanthi, O., & Reddy, M. S. (2012). Enhanced AES algorithm. International Journal of Computer Applications in Engineering Sciences, 2, 114–118.

    Google Scholar 

  21. Subhashini, U., & Jagadeeswari, M. (2016). FPGA based encryption algorithm for secure communication. International Journal of Innovative Research in Science, Engineering and Technology, 5, 8707–8714.

    Google Scholar 

  22. Toubal, A., Bengherbia, B., Zmirli, M. O., & Guessoum, A. (2020). FPGA implementation of a wireless sensor node with built-in security coprocessors for secured key exchange and data transfer. Measurement, 153, 1–16. https://doi.org/10.1016/j.measurement.2019.107429

    Article  Google Scholar 

  23. Elbirt, A.J., Yip, W., Chetwynd, B., & Paar, C. (2000). An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In: Proceedings of the third advanced encryption standard candidate conference, national institute of standards and technology (NIST), pp. 13–27, New York.

  24. Yoo, S. M., Kotturi, D., Pan, D. W., & Blizzard, J. (2005). An AES crypto chip using a high-speed parallel pipelined architecture. Microprocessors and Microsystems, 29, 317–326. https://doi.org/10.1016/j.micpro.2004.12.001

    Article  Google Scholar 

  25. Adib, S. E., & Raissouni, N. (2012). AES encryption algorithm hardware implementation: throughput and area comparison of 128, 192 and 256-bits key. International Journal of Reconfigurable and Embedded Systems, 1(2), 67–74.

    Google Scholar 

  26. Wang, Y., & Ha, Y. (2013). FPGA-based 40.9-Gbits/s masked AES with area optimization for storage area network. IEEE Transactions on Circuits and Systems-II: Express Briefs, 60(1), 36–40. https://doi.org/10.1109/TCSII.2012.2234891

    Article  Google Scholar 

  27. Neenu, S., & Bonifus, P. L. (2016). Design of AES architecture with area and speed tradeoff. Elsevier Procedia Technology, 24, 1135–1140.

    Article  Google Scholar 

  28. Nuray, A., Beuchat, J. L., Okamoto, E., San, I., & Yamazaki, T. (2017). A low-area unified hardware architecture for the AES and the cryptographic hash function Grostl. Journal of Parallel and Distributed Computing, 106, 106–120. https://doi.org/10.1016/j.jpdc.2017.01.029

    Article  Google Scholar 

  29. Guruprasad, S.P., & Chandrasekar, B.S. (2018). An evaluation framework for security algorithms performance realization on FPGA. In: Proceedings of the 2018 IEEE international conference on current trends in advanced computing, pp. 1–6, Bangalore, India.

  30. Nabil, M., Khalaf, A. A. M., & Hassan, S. M. (2020). Design and implementation of pipelined and parallel AES encryption systems using FPGA. Indonesian Journal of Electrical Engineering and Computer Science, 20(1), 287–299. https://doi.org/10.11591/ijeecs.v20.i1.pp287-299

    Article  Google Scholar 

  31. Kumar, T. M., Reddy, K. S., Rinaldi, S., Parameshachari, B. D., & Arunachalam, K. (2021). A low area high speed FPGA implementation of AES architecture for cryptography application. Electronics, 10(2023), 1–22. https://doi.org/10.3390/electronics10162023

    Article  Google Scholar 

  32. Sudarshan, T.S.B., Mir, R.A., & Vijayalakshmi, S. (2005). DRIL-A flexible architecture for Blowfish algorithm encryption using dynamic reconfiguration, replication, inner-loop pipelining, loop folding techniques. Lecture notes in computer science (including subseries lecture notes in artificial intelligence and lecture notes in bioinformatics). LCNS, pp. 625–639. Springer Verlag.

  33. Karthigaikumar, P., & Baskaran, K. (2010). Partially pipelined VLSI implementation of blowfish encryption/decryption algorithm. International Journal of Image and Graphics, 10(3), 327–341.

    Article  MathSciNet  Google Scholar 

  34. Kurniawan, N.P., Purwanto, Y., & Darlis, D. (2014). An implementation of data encryption for internet of things using blowfish algorithm on FPGA. In: Proceedings of the 2nd international conference on information and communication technology, IEEE, pp. 75–79, Bandung, Indonesia. https://doi.org/10.1109/ICoICT.2014.6914043

  35. Oukili, S., & Bri, S. (2016). High throughput parallel implementation of blowfish algorithm. International Journal of Applied Mathematics and Information Sciences, 10(6), 2087–2092.

    Article  Google Scholar 

  36. Suresh, M., & Neema, M. (2016). Hardware implementation of blowfish algorithm for the secure data transmission in internet of things. Elsevier Procedia Technology, 25, 248–255. https://doi.org/10.1016/j.protcy.2016.08.104

    Article  Google Scholar 

  37. Bansal, V. P., & Jassal, P. S. (2016). Synthesis and analysis of 64-bit blowfish algorithm using VHDL. International Journal of Engineering Sciences, 17(1), 316–322.

    Google Scholar 

  38. Chatterjee, S.R., Majumder, S., & Pramanik, B. (2014). FPGA implementation of pipelined blowfish algorithm. In: Proceedings of 5th international symposium electronic system design, pp. 208–209. https://doi.org/10.21817/ijet/2017/v9i2/170902320.

  39. Nalawade, S., & Gawali, D.H. (2017). Design and implementation of blowfish algorithm using reconfigurable platform. In: Proceedings of the 2017 international conference on recent innovations in signal processing and embedded systems, IEEE, pp. 479–484, Bhopal, India.

  40. Russell. (2019). Nandland: What is setup and hold time in an FPGA? Retrieved 25 May 2019 from https://www.nandland.com/articles/setup-and-hold-time-in-an-fpga.html

  41. Xilinx, Inc. (2015). Zynq-7000 all programmable SoC overview. Product specification, DS190, v(1.8), USA.

  42. Ahmad, R., Kho, D., Abd Manaf, A., & Ismail, W. (2019). Parallel-pipelined-memory-based blowfish design with reduced FPGA utilization for secure ZigBee real-time transmission. Wireless Personal Communications, 104, 471–489. https://doi.org/10.1007/s11277-018-6031-8

    Article  Google Scholar 

  43. Xilinx, Inc. (2017). User guide: Power analysis and optimization, UG907, v2017.3, USA.

Download references

Funding

This research was financially supported by the Universiti Sains Malaysia Short Term Research Grant (Project No. 304/PCEDEC/6315464).

Author information

Authors and Affiliations

  1. Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, 14300, Nibong Tebal, Pulau Pinang, Malaysia

    Rafidah Ahmad, Mohamad Faiz Mohamed Omar & Jagadheswaran Rajendran

  2. Auto-ID Laboratory, School of Electrical & Electronic Engineering, Engineering Campus, Universiti Sains Malaysia, 14300, Nibong Tebal, Pulau Pinang, Malaysia

    Widad Ismail

Authors
  1. Rafidah Ahmad
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Mohamad Faiz Mohamed Omar
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jagadheswaran Rajendran
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Widad Ismail
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Conceptualization: RA, WI; Methodology: RA; Formal analysis and investigation: RA, MFMO; Writing—original draft preparation: RA; Writing—review and editing: JR, WI; Resources: RA; Supervision: WI.

Corresponding author

Correspondence to Rafidah Ahmad.

Ethics declarations

Conflict of interest

The authors have no conflicts of interest to declare that are relevant to the content of this article.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ahmad, R., Mohamed Omar, M.F., Rajendran, J. et al. Performance Analysis of Enhanced AES-128 and Blowfish Algorithms Through Parallel-Pipelined-Memory Techniques. Wireless Pers Commun 127, 3615–3635 (2022). https://doi.org/10.1007/s11277-022-09933-2

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-022-09933-2

Keywords

Search

Navigation