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A Novel Digital Logic for Bit Reversal and Address Generations in FFT Computations

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Abstract

The Fast Fourier Transform and Inverse Fast Fourier Transform are high efficient algorithm that have wide a range of Digital Signal Processing (DSP) and telecommunication based applications. The FFT/IFFT structure with any number of complex valued input/output can be categorized as Decimation In Frequency (DIF) and Decimation In Time (DIT) decompositions. During Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) implementations, both these decompositions have advantages and disadvantages of its own. Unfortunately, the input sequence of DIT algorithm and output sequence of DIF algorithm is in bit reversed order, which makes it essential to convert the sequence into the natural order bit sequence. The goal is to convert the input samples in natural order into output samples in bit reversed order and to generate address locations for storage of intermediate stage results in the FFT/IFFT computation. A hardware scheme for bit reversal for variable length (8 ~ 64) pipelined FFT/IFFT processor to facilitate the continuous serial data flow and memory scheduling for address generations of memory for each stages in a radix-2 FFT/IFFT processor, based on a novel digital number system logic, is proposed. The proposed logic has basic operations such as shifting, one’s complement, two’s complement and additions. The proposed logic promises an area efficient, low power, high speed hardware implementation required for pipelined FFT/IFFT algorithms. The proposed variable length bit reversal architecture consumes a power of 65.46 µW and occupies an area of 2615.09 µm2 with a delay of 537 ps when implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology library.

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The authors declare that [the/all other] data supporting the findings of this study are available within the article [and its supplementary information files].

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The author(s) received no financial support for the research, authorship, and/or publication of this article.

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  1. School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, India

    Konguvel Elango

  2. Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai, 600044, India

    Kannan Muniandi

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  1. Konguvel Elango
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  2. Kannan Muniandi
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Correspondence to Konguvel Elango.

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Elango, K., Muniandi, K. A Novel Digital Logic for Bit Reversal and Address Generations in FFT Computations. Wireless Pers Commun 128, 1827–1838 (2023). https://doi.org/10.1007/s11277-022-10021-8

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