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Implementation of Programmable Finite Impulse Response Filter Using Modified Computation Sharing Multiplier for Hearing Aids

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Abstract

Filters for digital hearing devices utilize extensively different criteria than those designed for other applications. The device for this application requires miniature size and high performance. In fixed coefficient and programmable filter implementations, FIR filtering is constructed using a sequence of multiplications and additions along with delay elements. In this filter, the multipliers are used for coefficient and input multiplication; the adders are used for accumulation and the delay elements are necessary for storing the final accumulated result. The number of delay units, adders and multipliers depends on the number of orders while the size of these elements is based on the word length. The major area of the FIR filter is occupied by Multipliers. Therefore, improving the multiplier optimization will lead to an efficient FIR filter implementation. The multipliers are changed with shift and add circuits for the fixed coefficient FIR filter depending on the number of signed-power-of-two (SPT) terms existing in the fixed coefficient. In this research, the number of SPT terms in filter coefficients is reduced by the differential evolution algorithm. The number of adders required for the common subexpression (CSE) elimination algorithm is further minimized for efficient filter implementation. An area-efficient and high-speed FIR filter is proposed using Distributive arithmetic (DA) and implemented in the Xilinx Spartan3e FPGA environment. The proposed computation sharing multiplier (CSHM) based FIR on DA consumes less area in terms of FPGA slices and reduced delay when compared to the Existing CSHM. The area required for the proposed CSHM is reduced by 34% from the existing CSHM-based FIR Filter. Similarly, the performance of the Proposed FIR filter is increased by 24% more than the existing CSHM Method.

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References

  1. Parks, T., & McClellan, J. (1972). Chebyshev approximation for nonrecursive digital filters with linear phase. IEEE Transactions on Circuit Theory, 19(2), 189–194. https://doi.org/10.1109/TCT.1972.1083419

    Article  Google Scholar 

  2. McClellan, J., Parks, T., & Rabiner, L. (1973). A computer program for designing optimum FIR linear phase digital filters. IEEE Transactions on Audio and Electroacoustics, 21(6), 506–526. https://doi.org/10.1109/TAU.1973.1162525

    Article  Google Scholar 

  3. Samueli, H. (1989). An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients. IEEE Transactions on Circuits and Systems, 36(7), 1044–1047. https://doi.org/10.1109/31.31347

    Article  Google Scholar 

  4. Parhi, K. K. (2007). VLSI Digital Signal Processing. Wiley.

    Google Scholar 

  5. Aktan, M., Yurdakul, A., & Dundar, G. (2008). An algorithm for the design of low-power hardware-efficient FIR filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(6), 1536–1545. https://doi.org/10.1109/TCSI.2008.917997

    Article  MathSciNet  Google Scholar 

  6. Lim, Yong, & Parker, S. (1983). FIR filter design over a discrete powers-of-two coefficient space. IEEE Transactions on Acoustics, Speech, and Signal Processing, 31(3), 583–591. https://doi.org/10.1109/TASSP.1983.1164085

    Article  Google Scholar 

  7. Zhao, Q., & Tadokoro, Y. (1988). A simple design of FIR filters with powers-of-two coefficients. IEEE Transactions on Circuits and Systems, 35(5), 566–570. https://doi.org/10.1109/31.1785

    Article  Google Scholar 

  8. Lim, Y. C., Evans, J. B., & Liu, B. (1991). Decomposition of binary integers into signed power-of-two terms. IEEE Transactions on Circuits and Systems, 38(6), 667–672. https://doi.org/10.1109/31.81865

    Article  Google Scholar 

  9. Li, D., Song, J., & Lim, Y. C. A polynomial-time algorithm for designing digital filters with power-of-two coefficients.1993 IEEE International Symposium on Circuits and Systems (ISCAS), Chicago, IL, 1993, pp. 84–87 vol.1. doi: https://doi.org/10.1109/ISCAS.1993.393663

  10. Li, D. (1995). Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(7), 453–460. https://doi.org/10.1109/82.401168

    Article  MATH  Google Scholar 

  11. Dempster, A. G., & Macleod, M. D. (1995). Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(9), 569–577. https://doi.org/10.1109/82.466647

    Article  MATH  Google Scholar 

  12. Hartley, R. I. (1996). Subexpression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(10), 677–688. https://doi.org/10.1109/82.539000

    Article  Google Scholar 

  13. Cho, N. I., & Lee, S. U. (1998). Optimal design of finite precision FIR filters using linear programming with reduced constraints. IEEE Transactions on Signal Processing, 46(1), 195–199. https://doi.org/10.1109/78.651214

    Article  Google Scholar 

  14. Chen, C.-L., & Willson, A. N. (1999). A trellis search algorithm for the design of FIR filters with signed-powers-of-two coefficients. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46(1), 29–39. https://doi.org/10.1109/82.749079

    Article  Google Scholar 

  15. Yli-Kaakinen, J., & Saramaki, T. (2001) A systematic algorithm for the design of multiplierless FIR filters. In: ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), Sydney, NSW, 2001, pp. 185–188 vol. 2. doi: https://doi.org/10.1109/ISCAS.2001.921038

  16. Xu, F., Chang, C. H., & Jong, C. C. (2007). Design of low-complexity FIR filters based on signed-powers-of-two coefficients with reusable common subexpressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(10), 1898–1907. https://doi.org/10.1109/TCAD.2007.895615

    Article  Google Scholar 

  17. Shi, D., & Yu, Y. J. (2011). Design of linear phase FIR filters with high probability of achieving minimum number of adders. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(1), 126–136. https://doi.org/10.1109/TCSI.2010.2055290

    Article  MathSciNet  MATH  Google Scholar 

  18. Ye, W. B., & Yu, Y. J. (2015). Two-step optimization approach for the design of multiplierless linear-phase FIR filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(5), 1279–1287. https://doi.org/10.1109/TCSI.2015.2415178

    Article  MathSciNet  MATH  Google Scholar 

  19. Choo, H., Muhammad, K., & Roy, K. (2004). Complexity reduction of digital filters using shift inclusive differential coefficients. IEEE Transactions on Signal Processing, 52(6), 1760–1772. https://doi.org/10.1109/TSP.2004.827177

    Article  Google Scholar 

  20. Benvenuto, N., Marchesi, M., & Uncini, A. (1992). Applications of simulated annealing for the design of special digital filters. IEEE Transactions on Signal Processing, 40(2), 323–332. https://doi.org/10.1109/78.124942

    Article  Google Scholar 

  21. Karaboga, N., & Cetinkaya, B. (2005). Performance comparison of genetic and differential evolution algorithms for digital FIR filter design. Advances in Information Systems, 3261, 482–488.

    Article  Google Scholar 

  22. Nurhan, K., & Bahadir, C. (2006). Design of digital fir filters using differential evolution algorithm. Circuits, Systems and Signal Processing, 25(5), 649–660. https://doi.org/10.1007/s00034-005-0721-7

    Article  MathSciNet  MATH  Google Scholar 

  23. Vasundhara, D., Mandal, R., & Ghoshal, S. (2014). Digital FIR filter design using fitness based hybrid adaptive differential evolution with particle swarm optimization. Natural Computing, 13(1), 55–64.

    Article  MathSciNet  Google Scholar 

  24. Storn, R., & Price, K. (1997). Differential evolution a simple and efficient heuristic for global optimization over continuous spaces. Journal of Global Optimization, 11(4), 341–359.

    Article  MathSciNet  MATH  Google Scholar 

  25. imate Multiplier Design Based on Input Distribution and Polarity, vol. 1(1): pp. 545–551,2022

  26. Kumm, M., Volkova, A., & Filip, S. I. (2022). Design of optimal multiplierless FIR filters with minimal number of adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., 1(1), 1–15.

    Google Scholar 

  27. Kaiser, J., & Hamming, R. (1977). Sharpening the response of a symmetric nonrecursive filter by multiple use of the same filter. IEEE Transactions on Acoustics, Speech, and Signal Processing, 25(5), 415–422. https://doi.org/10.1109/TASSP.1977.1162980

    Article  MATH  Google Scholar 

  28. Tang, Z., Zhang, J., & Min, H. (2002). A high-speed, programmable, CSD coefficient FIR filter. IEEE Transactions on Consumer Electronics, 48(4), 834–837. https://doi.org/10.1109/TCE.2003.1196409

    Article  Google Scholar 

  29. Park, J., Woopyo Jeong, H., Mahmoodi-Meimand, Y. W., Choo, H., & Roy, K. (2004). Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE Journal of Solid-State Circuits, 39(2), 348–357. https://doi.org/10.1109/JSSC.2003.821785

    Article  Google Scholar 

  30. Mahesh, R., & Vinod, A. P. (2010). New reconfigurable architectures for implementing FIR Filters with low complexity. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(2), 275–288. https://doi.org/10.1109/TCAD.2009.2035548

    Article  Google Scholar 

  31. Padmapriya, S., & Prabha, V. L. (2015). Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing. Microprocessors and Microsystems, 39(7), 521–528.

    Article  Google Scholar 

  32. Reddy, K. S., & Sahoo, S. K. (2015). An approach for FIR Flter coefficient optimization, using differential evolution algorithm. AEU - International Journal of Electronics and Communications, 69(1), 101–108.

    Article  Google Scholar 

  33. Park, J., Woopyo Jeong, H., Mahmoodi-Meimand, Y. W., Choo, H., & Roy, K. (2004). Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE Journal of Solid-State Circuits, 39(2), 348–357. https://doi.org/10.1109/JSSC.2003.821785

    Article  Google Scholar 

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  1. Department of Electronics and Communication Engineering, Velammal Engineering College, Anna University, Chennai, Tamil Nadu, India

    V. Magesh

  2. Department of Computer Science Engineering, Velammal Engineering College, Anna University, Chennai, Tamil Nadu, India

    N. Duraipandian

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Magesh, V., Duraipandian, N. Implementation of Programmable Finite Impulse Response Filter Using Modified Computation Sharing Multiplier for Hearing Aids. Wireless Pers Commun 129, 255–270 (2023). https://doi.org/10.1007/s11277-022-10094-5

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