Skip to main content
SpringerLink
Log in

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

The circuit design in the system on a chip (SoC) is very difficult task during the physical design of a chip. Considering the fact of increasing complexity in the physical design, an efficient timing optimization methodology is needed. The conventional timing convergence methodology is inefficient at many points due to its poor design convergence and it performs timing optimization only by re-synthesizing the data path of the design. However, few design cases require the choice of Engineering Change Order (ECO) technique and clock-path timing optimization technique to meet the design convergence. In this research work, an Improved ECO (IECO) framework model is proposed. This proposed framework model suggests both data path and clock path timing optimization techniques with improved ECO patches. Both SOC design and benchmark circuitries are implemented in 14 nm technology node. Synopsys primetime and IC compiler tools have been used for this research work. For the considered SOC design, the conventional flow improves violation path fixing to 96.43%, unified ECO fixes 97.74% of violating path whereas the proposed framework fixed almost 99.07% of violation path within two iterations. The proposed framework model is tested in IWLS 256 tap FIR filter and ISCAS C2670 benchmark circuitries as a result 97.96 and 97.01% of violating path are fixed by proposed method.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Data Availability

Data sharing not applicable to this article.

References

  1. Khailany, B., Krimer, E., Venkatesan, R., Clemons, J., Emer, J.S., Fojtik, M., Klinefelter, A., et al. (2018). A modular digital VLSI flow for high-productivity SoC design. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), IEEE, pp. 1–6.

  2. Kamakshi, A.D., Fojtik, M., Khailany, B., Kudva, S., Zhou, Y. and Calhoun, B.H. (2016). Modeling and analysis of power supply noise tolerance with fine-grained GALS adaptive clocks. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 75–82.

  3. Dai, H., Liu, Y., Niu, J. and Ou, P. (August 13, 2019). Static timing analysis in circuit design. U.S. Patent, 10, 380,285.

  4. Blaauw, D., Zolotov, V., & Sundareswaran, S. (2002). Slope propagation in static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(10), 1180–1195.

    Article  Google Scholar 

  5. Chen, G., Onodera, H. and Tamaru, K. (1996). Timing and power optimization by gate sizing considering false path. In Proceedings of the Sixth Great Lakes Symposium on VLSI, IEEE, pp. 154–159.

  6. Hassoun, S., Cromer, C., & Calvillo-Gámez, E. (2003). Static timing analysis for level-clocked circuits in the presence of crosstalk. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(9), 1270–1277.

    Article  Google Scholar 

  7. Amin, C.S., Menezes, N., Killpack, K., Dartu, F., Choudhury, U., Hakim, N. and Ismail, Y. I. (2005). Statistical static timing analysis: How simple can we get? In Proceedings of the 42nd annual Design Automation Conference, pp. 652–657.

  8. Agarwal, A., Chopra, K., Blaauw, D. and Zolotov, V. (2005). Circuit optimization using statistical static timing analysis. In Proceedings. 42nd Design Automation Conference, pp. 321–324.

  9. Vygen, J. (2006). Slack in static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(9), 1876–1885.

    Article  Google Scholar 

  10. Kim, M. H. (April 13, 2010). Engineering change order cell and method for arranging and routing the same. U.S. Patent, 7, 698,680.

  11. Oh, N., Fallah-Tehrani, P. and Kasnavi, A. (June 14, 2011). Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques. U.S. Patent, 7,962,876.

  12. Chen, H. T., Chang, C. C., & Hwang, T. T. (2010). Reconfigurable ECO cells for timing closure and IR drop minimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1686–1695.

    Article  Google Scholar 

  13. Ho, K. H., Chen, Y. P., Fang, J. W., & Chang, Y. W. (2010). ECO timing optimization using spare cells and technology remapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5), 697–710.

    Article  Google Scholar 

  14. Lee, N.Z., Kravets, V.N. and Jiang, J.R.R. (2017). Sequential engineering change order under retiming and resynthesis. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 109–116.

  15. Hung, J. H., Lin, Y. C., Cheng, W. K., & Hsieh, T.-M. (2016). Unified approach for simultaneous functional and timing ECO. IET Circuits, Devices & Systems, 10(6), 514–521.

    Article  Google Scholar 

  16. Shanthala, L., & Jayagowri, R. (2017). Simultaneous data path and clock path engineering change order for efficient timing closure in complex SOC. Journal of VLSI and Signal Processing, 7, pp. 35–41.

  17. You, D.S., Yuan, G.J. and Shen, H. (2012). A path-matching timing optimization in physical design for DDR port of a global switch chip. In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp. 1–3.

  18. Xu, X., Shah, N., Evans, A., Sinha, S., Cline, B. and Yeric, G. (2017). Standard cell library design and optimization methodology for ASAP7 PDK. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 999–1004.

  19. Jiang, J.-H.R., Kravets, V.N., and Lee, N.-Z. (2020). Engineering change order for combinational and sequential design rectification. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, pp. 726–731.

  20. Ho, K.-H., Jiang, J.-H.R., & Chang, Y.-W. (2012). TRECO: Dynamic technology remapping for timing engineering change orders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(11), 1723–1733.

    Article  Google Scholar 

  21. Xie, F., and Wan, P. (2016). Clock tree synthesis and optimization in BES1300 IC Smart Card. In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 846–848.

  22. Terapasirdsin, A., & Kiattisin, S. (2020). Crosstalk-aware global routing in VLSI design by using a shuffled frog-leaping algorithm. Journal of Mobile Multimedia, 221-244. https://doi.org/10.13052/jmm1550-4646.161211

    Article  Google Scholar 

  23. Jiang, J. H. R., Kravets, V. N. and Lee, N. Z. (2020). Engineering change order for combinational and sequential design rectification. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, pp. 726–731.

  24. Correale Jr, A. and Goodall III, W. (2019). Engineering change order (eco) cell architecture and implementation. U.S. (2019). Patent Application 16/181,456, filed May 9.

  25. Seo, J. W., & Dal-Hee, L. E. E. (2019). Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell. U.S. Patent 10, 192, 860, issued January 29.

  26. Khursheed, A., & Khare, K. (2020). Optimized buffer insertion for efficient interconnects designs. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 33(5), e2748.

  27. Yang, Z., Serafy, C. and Srivastava, A. (2016). ECO based placement and routing framework for 3D FPGAs with micro-fluidic cooling. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, pp. 199–199.

  28. Fee, M., Frishmuth, R.J., Kusko, M.P. and Lichtenau, C. (2018). Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry. U.S. Patent 9,923,579, issued March 20.

Download references

Funding

No funding is provided for the preparation of manuscript.

Author information

Authors and Affiliations

  1. Centre for Nanoelectronics and VLSI Design, School of Electronics Engineering, Vellore Institute of Technology, Chennai Campus, Chennai, Tamil Nadu, 600127, India

    S. Umadevi

  2. Intel Technologies India Pvt. Ltd, Bangalore, Karnataka, 560037, India

    Sruthi Venkatesh

Authors
  1. S. Umadevi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sruthi Venkatesh
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors have equal contributions in this work.

Corresponding author

Correspondence to S. Umadevi.

Ethics declarations

Conflict of interest

Authors *1S.Umadevi & 2Sruthi Venkatesh, declares that they have no conflict of interest.

Consent to Participate

All the authors involved have agreed to participate in this submitted article.

Consent to Publish

All the authors involved in this manuscript give full consent for publication of this submitted article.

Ethical Approval

This article does not contain any studies with human participants or animals performed by any of the authors.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Umadevi, S., Venkatesh, S. Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design. Wireless Pers Commun 133, 699–724 (2023). https://doi.org/10.1007/s11277-023-10789-3

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-023-10789-3

Keywords

Search

Navigation