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An approach to instruction set compiled simulator development based on a target processor C compiler back-end design

  • SI: Engineering of Computer-Based Systems
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Abstract

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge related to compilers and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented showing that this approach has great potential.

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Authors and Affiliations

  1. Faculty of Technical Sciences, University of Novi Sad, 21000 , Novi Sad, Serbia

    Miodrag Djukic, Nenad Cetic, Radovan Obradovic & Miroslav Popovic

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  1. Miodrag Djukic
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  2. Nenad Cetic
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  3. Radovan Obradovic
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  4. Miroslav Popovic
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Correspondence to Miroslav Popovic.

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Manuscript received (insert date of submission if desired). Please note that all acknowledgments should be placed at the end of the paper, before the bibliography.

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Djukic, M., Cetic, N., Obradovic, R. et al. An approach to instruction set compiled simulator development based on a target processor C compiler back-end design. Innovations Syst Softw Eng 9, 135–145 (2013). https://doi.org/10.1007/s11334-013-0220-0

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