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Formal verification of SysML diagram using case studies of real-time system

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Abstract

System and software engineers use SysML models for the graphical modeling of the embedded systems. The SysML models are inadequate to express the discrete controllers with continuously evolving variables. The real-time constraints such as discrete and continuous dynamics are considered to be an important aspect in embedded systems. The lack of support of real-time aspect in SysML model can lead to inexplicit modeling of the embedded systems. The imprecise modeling could cause catastrophic results when an embedded system gets operational. In this paper, we propose hybrid automata-based semantics that supports the discrete and continuous behavior in upgraded SysML block diagram. The upgraded SysML block diagram is used for the modeling of the embedded system. Furthermore, we use model checker PRISM for the early design verification of upgraded SysML block diagram. Finally, we demonstrate the effectiveness of our proposed approach with the help of two case studies “temperature control system” and “water level control system”.

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  1. National University of Sciences and Technology, NUST Campus, H-12, Islamabad, Pakistan

    Sajjad Ali

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  1. Sajjad Ali
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Correspondence to Sajjad Ali.

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Ali, S. Formal verification of SysML diagram using case studies of real-time system. Innovations Syst Softw Eng 14, 245–262 (2018). https://doi.org/10.1007/s11334-018-0318-5

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  • DOI: https://doi.org/10.1007/s11334-018-0318-5

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