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Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

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Abstract

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.

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References

  1. Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191

    Article  MathSciNet  Google Scholar 

  2. Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532

    Article  MathSciNet  Google Scholar 

  3. Taraphdar C, Chattopadhyay T, Roy JN (2010) Mach-Zehnder interferometer-based all-optical reversible logic gate. Opt Laser Technol 42(2):249–259

    Article  Google Scholar 

  4. Das JC, De D (2016) Optimized design of reversible gates in quantum dot-cellular automata: a review. Rev Theor Sci 4(3):279–286

    Article  Google Scholar 

  5. Das JC, De D (2017) Circuit switching with quantum-dot cellular automata. Nano Commun Netw 14:16–28

    Article  Google Scholar 

  6. Ren J, Semenov VK (2011) Progress with physically and logically reversible superconducting digital circuits. IEEE Trans Appl Supercond 21(3):780–786

    Article  Google Scholar 

  7. Bandyopadhyay S, Balandin A, Roychowdhury VP, Vatan F (1998) Nanoelectronic implementations of reversible and quantum logic. Superlattices Microstruct 23(3–4):445–464

    Article  Google Scholar 

  8. Toffoli T (1980) Reversible computing. In: Lecture notes in computer science (ICALP 1980), vol 85, pp 632–644

  9. Feynman RP (1982) Simulating physics with computers. Int J Theor Phys 21(6):467–488

    Article  MathSciNet  Google Scholar 

  10. Fredkin E, Toffoli T (2006) Conservative logic. Int J Theor Phys 21(3–4):219–253

    MathSciNet  MATH  Google Scholar 

  11. Peres A (1985) Reversible logic and quantum computers. Phys Rev A 32(6):3266

    Article  MathSciNet  Google Scholar 

  12. Sultana M, Chaudhuri A, Sengupta D, Chaudhuri A (2018) Toffoli Netlist and QCA implementations for existing four variable reversible gates—a comparative analysis. Microsyst Technol 25:1987–2009

    Article  Google Scholar 

  13. Sultana M, Chaudhuri A, Sengupta D, Chaudhuri A (2018) Logic design and quantum mapping of a novel four variable reversible s2c2 gate. In: Annual convention of computer society of India (CSI 2017), Springer, Kolkata. pp 416–427

  14. Chaudhuri A, Sultana M, Sengupta D, Chaudhuri C, Chaudhuri A (2018) A reversible approach to two’s complement addition using a novel reversible TCG Gate and its 4 dot 2 electron QCA architecture. Microsyst Technol 25:1965–1975

    Article  Google Scholar 

  15. Noorallahzadeh M, Mosleh M (2019) Efficient designs of reversible latches with low quantum cost. IET Circuits Devices Syst 13(6):806–815

    Article  Google Scholar 

  16. Zulehner A, Wille R (2018) One-pass design of reversible circuits: combining embedding and synthesis for reversible logic. IEEE Trans Comput Aided Des Integr Circuits Syst 37(5):996–1008

    Google Scholar 

  17. Mondal S, Ghosh M, Datta K, Mukhopadhyay D, Dutta P (2019) A QCA design and energy analysis of binary semaphore with a comprehensive case study. Innov Syst Softw Eng 15:343–354

    Article  Google Scholar 

  18. Datta K, Sengupta I, Rahaman H (2015) A post-synthesis optimization technique for reversible circuits exploiting negative control lines. IEEE Trans Comput 64(4):1208–1214

    Article  MathSciNet  Google Scholar 

  19. IEEE Computer Society (2008, August) IEEE standards for floating-point arithmetic 754-2008

  20. Morrison M, Ranganathan N (2011) Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter. In: 11th IEEE international conference on nanotechnology, Portland, OR, USA. pp 1445–1449

  21. Khan MH, Perkowski M (2011) Synthesis of reversible synchronous counters. In: 41st IEEE international symposium on multiple-valued logic, Tuusula, Finland. pp 242–247

  22. Rajmohan V, Ranganathan V (2011) Design of counters using reversible logic. In: 3rd international conference on electronics computer technology, Kanyakumari, India. pp 138–142

  23. Singh R, Pandey MK (2016) Design and optimization of sequential counters using a novel reversible gate. In: International conference on computing, communication and automation (ICCCA), Noida, India. pp 1393–1398

  24. Naguboina GC, Anusudha K (2018) Realization and synthesis of ring counter and twisted ring counter using reversible logical computation with minimum quantum cost. In: International conference on inventive research in computing applications (ICIRCA), Coimbatore, India. pp 926–931

  25. Thapliyal H, Srinivas MB, Zwolinski M (2005) A beginning in the reversible logic synthesis of sequential circuits. In: Military and aerospace programmable logic devices. pp 1–5

  26. Hari S, Shroff S, Noor Mahammad S, Kamakoti V (2006) Efficient building blocks for reversible sequential circuit design. In: 49th IEEE international midwest symposium on circuits and systems, San Juan, Puerto Rico. pp 437–441

  27. Rice JE (2006) A new look at reversible memory elements. In: IEEE international symposium on circuits and systems, Island of Kos, Greece. pp 1243–1246

  28. Chuang ML, Wang CY (2008) Synthesis of reversible sequential elements. ACM J Emerg Technol Comput Syst 3(4):19:1–19:12

    Article  Google Scholar 

  29. Arabzadeh M, Saeedi M (2008–2013, version 2.5) Retrieved from RCViewer + : a viewer/analyzer for reversible and quantum circuits: http://ceit.aut.ac.ir/QDA/RCV.htm

  30. Joshi P, Sahu I (2017) A review paper on design of an asynchronous counter using novel reversible SG gate. In: International conference on innovative mechanisms for industry applications (ICIMIA), Bangalore, India. pp 617–621

  31. Rakshith S, Rakshith TR (2013) Contemplation of synchronous gray code counterand its variants using reversible logic gates. In: IEEE conference on information and communication technologies, Thuckalay, TN, India. pp 661–665

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Authors and Affiliations

  1. Department of Information Technology, Techno International New Town, Kolkata, India

    Mahamuda Sultana

  2. Department of Computer Science and Engineering, Techno Main Polytechnique (Techno Main Salt Lake), Kolkata, India

    Ayan Chaudhuri

  3. Department of Computer Science and Engineering, Techno International Batanagar, Kolkata, India

    Diganta Sengupta

  4. Department of Computer Science and Engineering, Maulana Abul Kalam Azad University of Technology, Kolkata, West Bengal, India

    Debashis De

  5. Veer Surendra Sai University of Technology, Sambalpur, Odisha, India

    Atal Chaudhuri

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  1. Mahamuda Sultana
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  2. Ayan Chaudhuri
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  3. Diganta Sengupta
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  4. Debashis De
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  5. Atal Chaudhuri
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Correspondence to Diganta Sengupta.

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Sultana, M., Chaudhuri, A., Sengupta, D. et al. Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist. Innovations Syst Softw Eng 17, 89–97 (2021). https://doi.org/10.1007/s11334-020-00369-0

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