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Efficient RT-Level Fault Diagnosis

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Abstract

Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. In this paper, we propose an RT-level diagnosis methodology capable of responding to these challenges. In the proposed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnostic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and significant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches.

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Authors and Affiliations

  1. Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA, 92093, U.S.A.

    Ozgur Sinanoglu & Alex Orailoglu

Authors
  1. Ozgur Sinanoglu
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  2. Alex Orailoglu
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Corresponding author

Correspondence to Ozgur Sinanoglu.

Additional information

The material herein is partly based upon our Workshop on RT Level Testing Presentation in 2004.

Ozgur Sinanoglu received a B.S degree in electrical engineering and a B.S. degree in computer engineering, both from Bogazici University, Istanbul, Turkey, in 1999. He received his M.S. and Ph.D. degrees in computer engineering from the University of California, San Diego, in 2001 and 2004, respectively. He is currently a senior DfT engineer at Qualcomm, Inc. His current research interests include RT-level test and low-power test of SOCs.

Alex Orailoglu received his B.S. degree cum laude from Harvard University in applied mathematics and his M.S. and Ph.D. degrees in computer science from the University of Illinois, Urbana-Champaign. Professor Orailoglu has been a faculty member at the University of California, San Diego since 1987, where he is currently professor of computer science and engineering. He previously held the position of Senior Member of Technical Staff at Gould Research Laboratories, Rolling Meadows, Illinois. His research interests include digital and analog test, fault tolerant computing, Computer-Aided Design and Embedded Processors.

Professor Orailoglu serves in the technical, organizing and/or steering committees of the major VLSI Test and Design Automation conferences and workshops. He is an associate editor of the IEEE Design and Test Magazine. He has served as the Technical Program Chair of the 1998 High Level Design Validation and Test (HLDVT) Workshop and as the General Chair of HLDVT’99. He is the founding chair of the Workshop on Application Specific Processors (WASP’02). He is also a member of the IEEE Test Technology Technical Council (TTTC) Executive Committee and currently serves as Vice Chair of TTTC and as Chair of the Test Technology Education Program subgroup. He has previously held the positions of Technical Activities Committee Chair and Planning Co-Chair of TTTC. He is a Golden Core member of the IEEE Computer Society.

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Sinanoglu, O., Orailoglu, A. Efficient RT-Level Fault Diagnosis. J Comput Sci Technol 20, 166–174 (2005). https://doi.org/10.1007/s11390-005-0166-2

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  • DOI: https://doi.org/10.1007/s11390-005-0166-2

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