Abstract
VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.
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This work was supported by the National High-Technology Development 863 Program of China under Grant No.2001AA111100. This paper is based on two preliminary papers presented at the IEEE 4th Workshop on RTL and High Level Testing, (WRTLT’03).
Li Shen was born in 1937. He graduated from the Department of Electrical Engineering, Zhejiang University, China, in 1959. Since then, he joined the staff of Institute of Computing Technology, Chinese Academy of Sciences, Beijing, where he is currently a professor. He is now an IEEE senior member. He has been engaged in research and design of digital circuits and computers for many years. From Oct. 1982 to Sept. 1984, he was a visiting scholar at Thomas J. Watson School of Engineering, Applied Science and Technology, State University of New York at Binghamton. From Oct. 1989 to Nov. 1991, he worked at Integrix Inc., Newbury Park, California, for several cooperative projects on workstation development and ASIC design. His research interests include soft computing, ASIC design, design for testability and fault testing.
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Shen, L. VFSim: Concurrent Fault Simulation at Register Transfer Level. J Comput Sci Technol 20, 175–186 (2005). https://doi.org/10.1007/s11390-005-0175-1
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DOI: https://doi.org/10.1007/s11390-005-0175-1