Abstract
This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.References
Chiu S S K, Papachristou C A. A built-in self-testing approach for minimizing hardware overhead. In Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors} (ICCD ‘91), Cambridge, MA, U.S.A., Oct. 14–16. 1991, pp.282–285,
Nicolici N, Al-Hashimi B M, Brown A D, Williams A C. BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2000, 19(11): 1375–1385.
Avra L. Allocation and assignment in high-level synthesis for self-testable data paths. In Proc. the International Test Conference, Nashville, 1991, pp.463–472.
Alvandpour A, Svensson C. A wire capacitance estimation technique for power consuming interconnections at high levels of abstraction. In Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS97), Louvain-la-Neuve, Belgium, 1997.
Hallberg J, Peng Z. Estimation and consideration of interconnection delays during high level synthesis. In Proc. the 24th Euromicro Conference, Vasteras, Sweden, Aug. 1998, Vol.1, pp.349–356.
Goel S K, Marinissen E J. Layout-driven SoC test architecture design for test time and wire length minimization. In Proc. the Design, Automation and Test in Europe, 2003, pp.738–743.
Reeves C R. Modern Heuristic Techniques for Combinatorial Problems. Blackwell Scientific Publications, 1993.
Mohamed A R, Peng Z, Eles P. BIST synthesis: An approach to resources optimization under test time constraints. In Proc. the 5th Design and Diagnostic of Electronic Circuits and Systems (DDECS2002), Brno, Czech Republic, 2002, pp.346–351.
Ghosh I, Jha N K, Bhawmik S. A BIST scheme for RTL circuits based on symbolic testability analysis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, 19(1): 111–128.
Ghosh I, Jha N K, Bhawmik S. A BIST scheme for RTL controller-data paths based on symbolic testability analysis. In Proc. the 35th ACM IEEE Design Automation Conference, San Francisco, CA, U.S.A., 1998, pp.554–559.
Moshnyaga V G, Tumaru K. A placement driven methodology for high-level synthesis of sub-micron ASICS. In International Symposium on Circuits and Systems (ISCAS’96), May 1996, pp.572–575.
M Tien-Chien Lee. High-Level Test Synthesis of Digital VLSI Circuits. Artech House, 1997.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Mohamed, A.R., Peng, Z. & Eles, P. A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. J Comput Sci Technol 20, 216–223 (2005). https://doi.org/10.1007/s11390-005-0216-9
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/s11390-005-0216-9