Abstract
Microarchitects should consider power consumption, together with accuracy, when designing a branch predictor, especially in embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB (Branch Target Buffer) selectively. To enable the selective access to the BTB, the PHT (Pattern History Table) in the proposed branch predictor is accessed one cycle earlier than the traditional PHT if the program is executed sequentially without branch instructions. As a side effect, two predictions from the PHT are obtained through one access to the PHT, resulting in more power savings. In the proposed branch predictor, if the previous instruction was not a branch and the prediction from the PHT is untaken, the BTB is not accessed to reduce power consumption. If the previous instruction was a branch, the BTB is always accessed, regardless of the prediction from the PHT, to prevent the additional delay/accuracy decrease. The proposed branch predictor reduces the power consumption with little hardware overhead, not incurring additional delay and never harming prediction accuracy. The simulation results show that the proposed branch predictor reduces the power consumption by 29–47%.
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This work was supported by the BK21 Project.
Cheol Hong Kim received the B.S. degree in computer engineering from Seoul National University, Seoul, Korea in 1998 and M.S. degree in 2000. He is currently a Ph.D. candidate in the Department of Electrical Engineering and Computer Science at Seoul National University. His research interests include computer architecture, low power system and multiprocessors.
Sung Woo Chung received the B.S. and M.S. degrees in computer engineering, and the Ph.D. degree in electrical and computer engineering from Seoul National University, Seoul, Korea in 1996, 1998, and 2003 respectively. He worked as an academic visitor for IBM T.J. Watson Research Center in Yorktown Heights, NY, USA from Jan. 2002 to July 2002. He worked as a senior engineer for Processor Architecture Laboratory in Samsung Electronics, Korea from Jan. 2003 to Feb. 2005. Now he is working as a Post-Doctor in Department of Computer Science, University of Virginia, USA. His research interests include microarchitecture, cache management, system architecture, parallel architecture and low-power design.
Chu Shik Jhon received the B.S. degree in applied mathematics from Seoul National University, Seoul, Korea in 1975, the M.S. degree in computer engineering from Korea Advanced Institute of Science and Technology, Daegeon, Korea in 1977, and the Ph.D. degree in computer engineering from the University of Utah in 1982. He was an associated professor in Computer Engineering Department at Iowa State University from 1983 to 1985. He is currently a professor in the Department of Electrical Engineering and Computer Science at Seoul National University. His research interests include computer architecture, parallel computing, and VLSI design automation.
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Kim, C.H., Chung, S.W. & Jhon, C.S. A Power-Aware Branch Predictor by Accessing the BTB Selectively. J Comput Sci Technol 20, 607–614 (2005). https://doi.org/10.1007/s11390-005-0607-y
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DOI: https://doi.org/10.1007/s11390-005-0607-y