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Micro-Task Processing in Heterogeneous Reconfigurable Systems

  • Special Section on Advanced Computer Systems Architecture
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Abstract

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

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Authors and Affiliations

  1. Department of Distributed Systems, Technical University of Hamburg-Harburg, Schwarzenbergstrasse 95, D-21073, Hamburg, Germany

    Sebastian Wallner

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  1. Sebastian Wallner
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Correspondence to Sebastian Wallner.

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Sebastian Wallner received the Dipl.-Inform. (M.Sc.) degree in computer science from the University of Hamburg, Germany, in 2000. In 2000, he joined the Department of Computer Engineering VI at the Technical University Hamburg-Harburg (TUHH) where he is currently pursuing his Ph.D. degree. His research interests include reconfigurable computing, heterogeneous computing systems, parallel computing architectures and lightweight cryptographic algorithms as well as embedded security.

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Wallner, S. Micro-Task Processing in Heterogeneous Reconfigurable Systems. J Comput Sci Technol 20, 624–634 (2005). https://doi.org/10.1007/s11390-005-0624-x

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  • DOI: https://doi.org/10.1007/s11390-005-0624-x

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