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Power Efficient Sub-Array in Reconfigurable VLSI Meshes

  • Special Section on Advanced Computer Systems Architecture
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Abstract

Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

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References

  1. Leighton T, Gamal A E. Wafer-scal integration of systoric arrays. IEEE Trans. Computers, May 1985, 34(5): 448–461.

    Google Scholar 

  2. Lam C W H, Li H F, Jakakumar R. A study of two approaches for reconfiguring fault-tolerant systoric array. IEEE Trans. Computers, June 1989, 38(6): 833–844.

    Article  Google Scholar 

  3. Koren I, Singh A D. Fault tolerance in VLSI circuits. Computer, July 1990, 23(7): 73–83.

    Article  Google Scholar 

  4. Chen Y Y, Upadhyaya S J, Cheng C H. A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors. IEEE Trans. Computers, 1997, 46(12): 1363–1371.

    Article  Google Scholar 

  5. Horita T, Takanami I. Fault-tolerant processor arrays based on the 1.5-track switches with flexible spare distributions. IEEE Trans. Computers, June 2000, 49(6): 542–552.

    Article  Google Scholar 

  6. Kuo S Y, Fuchs W K. Efficient spare allocation for reconfigurable arrays. IEEE Design and Test, Feb. 1987, 4(7): 24–31.

    Google Scholar 

  7. Wey C L, Lombardi F. On the repair of redundant RAM's. IEEE Trans. CAD of Integrated Circuits and Systems, Mar. 1987, 6(2): 222–231.

    Article  Google Scholar 

  8. Li Zhang. Fault-tolerant meshes with small degree. IEEE Trans. Computers, May 2002, 51(5): 553–560.

    Article  Google Scholar 

  9. Negrini R, Sami M Git et al. Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays. The MIT Press, 1989.

  10. Kuo S Y, Chen I Y. Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design, Oct. 1992, 11(10): 1289–1300.

    Article  Google Scholar 

  11. Low C P, Leong H W. On the reconfiguration of degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 1997, 16(10): 1213–1221.

    Article  Google Scholar 

  12. Low C P. An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. Computers, June 2000, 49(6): 553–559.

    Article  Google Scholar 

  13. Wu Jigang, Schroder Heiko, Srikanthan Thambipillai. New architecture and algorithms for degradable VLSI/WSI arrays. In Proc. 8th International Computing and Combinatorics Conference, Singapore, 2002, (COCOON'O2), Lecture Notes in Computer Science, Vol. 2387, Aug. 2002, pp.181–190.

  14. Aho A V, Hopcroft J E et al. The Design and Analysis of Computer Algorithms. Addison-Wesley, Reading, Mass., 1974.

    Google Scholar 

Download references

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Authors and Affiliations

  1. Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, 639798, Singapore

    Ji-Gang Wu & Thambipillai Srikanthan

Authors
  1. Ji-Gang Wu
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  2. Thambipillai Srikanthan
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Corresponding author

Correspondence to Ji-Gang Wu.

Additional information

Ji-Gang Wu has been with Nanyang Technological University (NTU), Singapore, since 2000. He is currently a research fellow in Centre for High Performance Embedded Systems. He received his B.S. degree in computational mathematics from Lanzhou University (China) in 1983 and his Ph.D. degree in computer software and theory from University of Science and Technology of China. He was an assistant professor and lecturer in Lanzhou University from 1983 to 1993. He was an associate professor in Yantai University (China) from 1993 to 2000. His research interests include VLSI design, hardware/software co-design and parallel computing.

Thambipillai Srikanthan has been with Nanyang Technological University (NTU), Singapore, since 1991, where he holds a joint appointment as Professor and Director of the Centre for High Performance Embedded Systems. He received his B.Sc. degree (Hons) in computer and control systems and Ph.D. degree in system modelling and information systems engineering from Coventry University, United Kingdom. His research interests include system integration methodologies, architectural translations of compute intensive algorithms, high-speed techniques for image processing and dynamic routing. He is a corporate member of the IEE and a senior member of the IEEE.

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Wu, JG., Srikanthan, T. Power Efficient Sub-Array in Reconfigurable VLSI Meshes. J Comput Sci Technol 20, 647–653 (2005). https://doi.org/10.1007/s11390-005-0647-3

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  • DOI: https://doi.org/10.1007/s11390-005-0647-3

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