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An Error Recoverable Structure Based on Complementary Logic and Alternating-Retry

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Abstract

Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online testing plus retrying structure. Obviously, although retry can mask transient or intermittent faults, it is useless for handling permanent faults generally. To solve this problem, this paper presents a novel dual modular redundancy (DMR) structure using complementary logic—alternating-complementary logic (CL-ACL) switching mode. During error-free operation, the CL-ACL structure operates by complementary logic mode. After an error is detected, it retries by alternating logic mode. If all errors belong to single or multiple temporary 0/1-error or stuck-at-error produced by one module, then these errors can be corrected effectively. The results obtained from the simulation validate the correctness of the CL-ACL structure. Analytic results show that the delay of the CL-ACL structure is dramatically less than that of a DMR structure using alternating-complementary logic mode.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tongji University, Shanghai, 200092, P.R. China

    Jian-Hui Jiang

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  1. Jian-Hui Jiang
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Correspondence to Jian-Hui Jiang.

Additional information

Supported by the National Natural Science Foundation of China under Grant No. 90207021.

Jian-Hui Jiang received his B.Eng., M.Eng. and D.Eng. degrees in 1985, 1988, and 1999, respectively. He is currently a professor of computer science and technology at Tongji University. He is serving as a member of the Editorial Board of the Journal of Circuits and Systems sponsored by Guangzhou Institute of Electronic Technology, Chinese Academy of Sciences. He is a member of Technical Committee on Fault-Tolerant Computing, China Computer Federation (CCF), and a member of Technical Committee on Embedded Systems and Single-Chip Microprocessor, Shanghai Computer Society. He has served on several program committees of national or international symposiums or workshops including IEEE WRTLT. He has coauthored two books and published more than 60 technical papers. His research interests include fault-tolerant computing, digital system design and testing, software reliability engineering, performance evaluation of computer systems, and distributed computing. He is a senior member of CCF.

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Jiang, JH. An Error Recoverable Structure Based on Complementary Logic and Alternating-Retry. J Comput Sci Technol 20, 885–894 (2005). https://doi.org/10.1007/s11390-005-0885-4

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  • DOI: https://doi.org/10.1007/s11390-005-0885-4

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