Abstract
This paper describes a test architecture for minimum number of test configurations in test of FPGA (Field Programmable Gate Array) LUTs (Look Up Tables). The test architecture includes a TPG (Test Pattern Generator) that is tested while it is generating test data for LEs (Logic Elements) that form the CUT (Circuit Under Test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (Output Response Analyzer) and having to perform many more reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.References
Metra C et al. Novel technique for testing FPGA. Design, Automation and Test in Europe, Palais des Congres Paris, France, 1998, pp.89–94.
Alderighi M, Gummati E, Piuri V, Sechi G. A FPGA based implementation of a fault tolerant neural architecture for photon identification. In Proc. the Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, USA, 1997, pp.166–172.
Renovell M, Figueras J, Zorian Y. Test of RAM-based FPGA: Methodology and application to the interconnect. In Proc. 15th VLSI Test Symp., Anaheim, USA, 1997, pp.230–237.
Stroud C, Wijesuriya S, Hamilton C, Abramovici M. Built-in self-test of FPGA interconnect. In Proc. the IEEE Int. Test Conf., Washington DC, USA, 1998, pp.404–411.
Sun X, Xu J, Trouborst P. Testing Xilinx XC4000 configurable logic blocks with carry logic modules. In Proc. the IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, USA, October 2001, pp.221–229.
Renovell M, Portal J M, Figueras J, Zorian Y. RAM-based FPGAs: A test approach for the configurable logic. In Proc. the Design, Automation and Test in Europe, Palais des Congres Paris, France, 1998, pp.82–88.
Huang W K, Meyer F J, Park N, Lombardi F. Testing memory modules in SRAM-based configurable FPGAs. In Proc. IEEE International Workshop on Memory Technology, Design and Test, San Jose, CA, USA, August 1997, pp.79–86.
Renovell M. SRAM-based FPGAs: A structural test approach. IEEE XI Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro, Brazil, Oct. 1998, pp.67–72.
Inoue T et al. Universal test complexity of field programmable gate arrays. In Proc. Asian Test Symp., Bangalore, India, 1995, pp.259–265.
Stroud C et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). In Proc. VLSI Test Symp., Princeton, NJ, USA, 1996, pp.387–392.
Altera Data Book. San Jose, USA, 2002.
The Programmable Logic Data Book. Xilinx Inc., 2000.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Atoofian, E., Navabi, Z. A Test Approach for Look-Up Table Based FPGAs . J Comput Sci Technol 21, 141–146 (2006). https://doi.org/10.1007/s11390-006-0141-6
Received:
Accepted:
Issue Date:
DOI: https://doi.org/10.1007/s11390-006-0141-6