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Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

  • Special Section on China AVS Standard
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Abstract

The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching), this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

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Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, P.R. China

    Li Zhang & Di Wu

  2. Graduate University of Chinese Academy of Sciences, Beijing, 100039, P.R. China

    Li Zhang

  3. Grandview Semiconductor (Beijing) Corporation, Beijing, 100039, P.R. China

    Don Xie

Authors
  1. Li Zhang
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  2. Don Xie
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  3. Di Wu
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Corresponding author

Correspondence to Li Zhang.

Additional information

Supported by the National High Technology Development 863 Program of China under Grant No. 2003AA1Z1290.

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Zhang, L., Xie, D. & Wu, D. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard. J Comput Sci Technol 21, 378–382 (2006). https://doi.org/10.1007/s11390-006-0378-0

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  • DOI: https://doi.org/10.1007/s11390-006-0378-0

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