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Design and Implementation of NAREGI SuperScheduler Based on the OGSA Architecture

  • Grid & Services Computing
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Abstract

NAREGI is a 5-year Japanese National Grid Project during 2003–2007, whose chief aim is to develop a set of grid middleware to serve as a basis for future e-Science. NAREGI also aims to lead the way in standardization of grid middleware, based on the OGSA architecture. Its super-scheduler is based on the proposed OGSA-EMS Architecture, in that it becomes the first working implementation that implements the documented component relationships within the OGSA-EMS architecture document v.1.0. Through the efforts and experience in the design and implementation, it has been confirmed that the documented OGSA-EMS architecture is quite feasible, but will require significant amount of refinement and speed improvements to finalize its detailed specifications. The super-scheduler also supports co-allocation across multiple sites to support automated execution of grid-based MPIs that execute across machines. Such a resource allocation requires sophisticated interactions between the OGSA-EMS components not covered in the current OGSA-EMS architecture, some of which are non-trivial. Overall, job scheduling with OGSA-EMS has proven to not only work, but also that its job allocation and execution time is within reasonable bounds.

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Authors and Affiliations

  1. Global Scientific Information and Computing Center, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo, 152-8550, Japan

    Satoshi Matsuoka

  2. Center for Grid Research and Development, National Institute of Informatics, 1-105, Kanda-Jinbocho, Chiyoda-ku, Tokyo, 101-0051, Japan

    Satoshi Matsuoka, Kazushige Saga & Hidemoto Nakada

  3. Linux Software Development Div., Server Systems Unit., Fujitsu Limited, 140 Miyamoto, Numazu-shi, Shizuoka, 410-0396, Japan

    Masayuki Hatanaka, Yasumasa Nakano, Yuji Iguchi & Toshio Ohno

  4. Grid Technology Research Center, National Institute of Advanced Industrial Science and Technology, 1-18-13 Sotokanda Chiyoda-ku, Tokyo, 101-0021, Japan

    Hidemoto Nakada

Authors
  1. Satoshi Matsuoka
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  2. Masayuki Hatanaka
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  3. Yasumasa Nakano
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  4. Yuji Iguchi
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  5. Toshio Ohno
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  6. Kazushige Saga
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  7. Hidemoto Nakada
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Corresponding author

Correspondence to Masayuki Hatanaka.

Additional information

Yasumasa Nakano received his B.Sc. degree from Tokyo University of Science in 1991. He joined Fujitsu Inc. in 1991, working mainly in the area of UNIX System V library/command for the VPP (vector parallel supercomputer). Since 2003 he has been involved with the NAREGI project.

Yuji Iguchigraduated from Yoshiwara Technical High School. He joined Fujitsu Inc. in 1981, working mainly in the area of supercomputing software. Since 2003 he has been involved with the NAREGI project.

Toshio Ohno received his B.Sc. degree from Toyama Univ. in 1989. He joined Fujitsu Inc. in 1989, working mainly in the area of supercomputing software. Since 2003 he has been involved with the NAREGI project.

Kazushige Saga received his M.Eng. degree from Meiji Univ. in 1981. He joined Fujitsu in 1981 and Fujitsu Labs in 1988, working mainly in the area of distributed computing systems. From 2002 to 2003, he was involved with the VizGrid project. He joined National Institute of Informatics in 2004, where he has been involved with NAREGI project. He is a member of IEICE, IPSJ, and JNNS.

Hidemoto Nakada received his Ph.D. degree in computer engineering from the University of Tokyo in 1995. He then joined and is currently working for the National Institute of Advanced Industrial Science and Technology, Grid Technology Research Center, as a Senior Research Scientist. He served as a visiting associate professor at Tokyo Institute of Technology from 2001 to 2006. He was one of the founding members of the Ninf GridRPC project, and has been working on various Grid projects including his involvement with NAREGI since 2003.

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Matsuoka, S., Hatanaka, M., Nakano, Y. et al. Design and Implementation of NAREGI SuperScheduler Based on the OGSA Architecture. J Comput Sci Technol 21, 521–528 (2006). https://doi.org/10.1007/s11390-006-0521-y

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  • DOI: https://doi.org/10.1007/s11390-006-0521-y

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