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Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation

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Abstract

Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF(2m using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is pesented. The architecture is optimized in order to minimize the silicon covered area (transistor count). The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF(2m).

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Authors and Affiliations

  1. Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taoyuan, County, 333

    Chiou-Yng Lee

  2. Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung

    Jenn-Shyong Horng & I-Chang Jou

Authors
  1. Chiou-Yng Lee
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  2. Jenn-Shyong Horng
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  3. I-Chang Jou
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Corresponding author

Correspondence to Chiou-Yng Lee.

Additional information

The work was supported in part by the “National Science Council” under Grant No. NSC-94-2218-E-262-003.

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Lee, CY., Horng, JS. & Jou, IC. Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation. J Comput Sci Technol 21, 887–892 (2006). https://doi.org/10.1007/s11390-006-0887-x

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  • DOI: https://doi.org/10.1007/s11390-006-0887-x

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