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Parallel Error Detection for Leading Zero Anticipation

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Abstract

The algorithm and its implementation of the leading zero anticipation (LZA) are very vital for the performance of a high-speed floating-point adder in today’s state of art microprocessor design. Unfortunately, in predicting “shift amount” by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.

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Authors and Affiliations

  1. Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, P.R. China

    Ge Zhang, Wei-Wu Hu & Zi-Chu Qi

  2. Graduate University of the Chinese Academy of Sciences, Beijing, 100039, P.R. China

    Ge Zhang, Wei-Wu Hu & Zi-Chu Qi

Authors
  1. Ge Zhang
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  2. Wei-Wu Hu
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  3. Zi-Chu Qi
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Corresponding author

Correspondence to Ge Zhang.

Additional information

Supported by the National High Technology Development 863 Program of China under Grant Nos. 2002AA111100 and the National Basic Research 973 Program of China under Grant No. 2005CB321600.

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Zhang, G., Hu, WW. & Qi, ZC. Parallel Error Detection for Leading Zero Anticipation. J Comput Sci Technol 21, 901–906 (2006). https://doi.org/10.1007/s11390-006-0901-3

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  • DOI: https://doi.org/10.1007/s11390-006-0901-3

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