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A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme

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Abstract

In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform (DWT) using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.

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Authors and Affiliations

  1. School of Computer Science, Xidian University, Xi’an, 710071, China

    Kai Liu

  2. National Key Laboratory of Integrated Service Networks, Xidian University, Xi’an, 710071, China

    Ke-Yan Wang, Yun-Song Li & Cheng-Ke Wu

Authors
  1. Kai Liu
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  2. Ke-Yan Wang
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  3. Yun-Song Li
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  4. Cheng-Ke Wu
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Correspondence to Kai Liu.

Additional information

Supported by the National Natural Science Foundation of China under Grant Nos. 60532060 and 60507012.

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Liu, K., Wang, KY., Li, YS. et al. A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme. J Comput Sci Technol 22, 661–672 (2007). https://doi.org/10.1007/s11390-007-9087-6

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  • DOI: https://doi.org/10.1007/s11390-007-9087-6

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