Skip to main content
Log in

New Model and Algorithm for Hardware/Software Partitioning

  • Regular Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O(nA) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Niemann R, Marwedel P. Hardware/software partitioning using integer programming. In Proc. the IEEE/ACM European Design Automation Conference (EDAC), Paris, France, March 1996, pp.473–479.

  2. Gupta R, Micheli G D. Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers, 1993, 10(3): 29–41.

    Article  Google Scholar 

  3. Gupta R K, Coelho C, De Micheli G. Synthesis and simulation of digital systems containing interacting hardware and software components. In Proc. the 29th ACM/IEEE Design Automation Conference, Los Alamitos, CA, USA, June 1992, pp.225–230.

  4. Ernst R, Henkel J, Benner T. Hardware-software co-synthesis for micro-controllers. IEEE Design and Test of Computer, 1993, 10(4): 64–75.

    Article  Google Scholar 

  5. Vahid F, Gajski D D, Gong J. A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. In Proc. IEEE/ACM European Design Automation Conference (EDAC), Paris, France, February 1994, pp.214–219.

  6. Vahid F, Gajski D D. Clustering for improved system-level functional partitioning. In Proc. the 8th International Symposium on System Synthesis, Cannes, France, September 1995, pp.28–33.

  7. Quan G, Hu X, Greenwood G W. Preference-driven hierarchical hardware/software partitioning. In Proc. IEEE International Conference on Computer Design, Austin, TX, USA, October 1999, pp.652–657.

  8. Srinivasan V, Radhakrishnan S, Vemuri R. Hardware software partitioning with integrated hardware design space exploration. In Proc. DATE’98, Paris, France, February 1998, pp.28–35.

  9. Niemann R, Marwedel P. An algorithm for hardware/software partitioning using mixed integer linear programming. Design Automation for Embedded Systems, Special Issue: Partitioning Methods for Embedded Systems, 1997, 2(2): 165–193.

    Article  Google Scholar 

  10. Weinhardt M. Integer programming for partitioning in software oriented codesign. Lecture Notes in Computer Science, 1995, 975: 227–234.

    Google Scholar 

  11. Peng Z, Kuchcinski K. An algorithm for partitioning of application specific system. In Proc. IEEE/ACM European Design Automation Conference (EDAC), Paris, February 1993, pp.316–321.

  12. Henkel J, Ernst R. An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. IEEE Trans. VLSI Sys., 2001, 9(2): 273–289.

    Article  Google Scholar 

  13. Eles P, Peng Z, Kuchcinski K, Dobolt A. System level hardware/software partitioning based on simulated annealing and tabu search. Design Automation for Embedded Systems, 1997, 2(1): 5–32.

    Article  Google Scholar 

  14. Karam S C, Ranga V. Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002, 10(3): 193–208.

    Article  Google Scholar 

  15. Madsen J, Grode J, Knudsen P V, Petersen M E, Haxthausen A. LYCOS: The Lyngby co-synthesis system. Design Automation for Embedded Systems, 1997, 2: 195–235.

    Article  Google Scholar 

  16. Wu Jigang, Srikanthan T. Low-complex dynamic programming algorithm for hardware/software partitioning. Information Processing Letters, 2006, 98: 41–46.

    Article  Google Scholar 

  17. Edwards S A, Lavagno L, Lee E A et al. Design of embedded systems: Formal models validation, and synthesis. In Proc. the IEEE, 1997, 85(3): 366–390.

  18. Vallejo M L, Lopez J C. On the hardware-software partitioning problem: System modeling and partitioning techniques. ACM Transactions on Design Automation of Electronic Systems, 2003, 8(3): 269–297.

    Article  Google Scholar 

  19. Pisinger D. Algorithms for knapsack problems [Dissertation]. University of Copenhagen, 1995.

  20. Arato P, Mann Z A, Orban A. Algorithmic aspects of hardware/software partitioning. ACM Transactions on Design Automation of Electronic Systems, 2005, 10(1): 136–156.

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Ji-Gang Wu.

Electronic supplementary material

Below is the link to the electronic supplementary material.

(PDF 78.1 kb)

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wu, JG., Srikanthan, T. & Zou, GW. New Model and Algorithm for Hardware/Software Partitioning. J. Comput. Sci. Technol. 23, 644–651 (2008). https://doi.org/10.1007/s11390-008-9160-9

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-008-9160-9

Keywords

Navigation