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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Abstract

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.

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Authors and Affiliations

  1. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Da Wang, Yu Hu, Hua-Wei Li & Xiao-Wei Li

  2. Graduate University of Chinese Academy of Sciences, Beijing, 100049, China

    Da Wang

Authors
  1. Da Wang
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  2. Yu Hu
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  3. Hua-Wei Li
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  4. Xiao-Wei Li
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Corresponding author

Correspondence to Xiao-Wei Li.

Additional information

This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010, and in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605, and in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476.

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Wang, D., Hu, Y., Li, HW. et al. Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23, 1037–1046 (2008). https://doi.org/10.1007/s11390-008-9193-0

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  • DOI: https://doi.org/10.1007/s11390-008-9193-0

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