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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Abstract

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.

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References

  1. Needham W. Microprocessor testing today. IEEE Design & Test of Computers, Jul.–Sept. 1998, 15(3): 56–57.

    Article  Google Scholar 

  2. Kusko M P, Robbins B J, Snethen T J, Song P. Foote T G, Huott W V. Microprocessor test and test tool methodology for the 500MHz IBM S/390 G5 chip. In Proc. Int. Test Conf. (ITC 98), Washington DC, USA, IEEE CS Press, 1998, pp.717–726.

  3. Abadir M, Dasgupta S. Microprocessor test and verification. IEEE Design & Test of Computers, Oct.–Dec. 2000, 17(4): 4–5.

    Google Scholar 

  4. Crouch A L et al. The test development for a third-version ColdFire microprocessors. IEEE Design & Test of Computers, Oct.–Dec. 2000, 17(4): 29–37.

    Article  MathSciNet  Google Scholar 

  5. Wu D M et al. An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor. In Proc. Int. Test Conf. (ITC 04), Charlotte, NC, USA, IEEE CS Press, 2004, pp.38–47.

  6. Tan P J et al. Testing of UltraSPARC T1 microprocessor and its challenges. In Proc. Int. Test Conf. (ITC 06), Santa Clara, CA, USA, IEEE CS Press, 2006, paper 16.1.

  7. Molyneaux R et al. Design-for-testability features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip. In Proc. Int. Test Conf. (ITC 07), Santa Clara, CA, USA, IEEE CS Press, 2007, paper 1.2.

  8. Sehgal A et al. Test cost reduction for the AMD Athlon processor using test partitioning. In Proc. Int. Test Conf. (ITC 07), Santa Clara, CA, USA, IEEE CS Press, 2007, paper 1.3.

  9. Lin X et al. High-frequency, at-speed scan testing. IEEE Design & Test of Computers, Sept.–Oct. 2003, 20(5): 17–25.

    Article  Google Scholar 

  10. Li Z et al. Microarchitecture and performance analysis of Godson-2 SMT processor. In Proc. Int. Conf. Computer Design (ICCD 06), San Jose, CA, USA, IEEE CS Press, 2006, pp.485–490.

  11. Hu W et al. Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology. Journal of Computing Science and Technology, Jan. 2007, 22(1): 1–14.

    Article  Google Scholar 

  12. Wang D et al. The design-for-testability features of a general purpose microprocessor. In Proc. Int. Test Conf. (ITC 07), Santa Clara, CA, USA, IEEE CS Press, 2007, paper 9.2.

  13. Cory B et al. Speed binning with path delay test in 150-nm technology. IEEE Design & Test of Computers, Sept.–Oct. 2003, 20(5): 41–45.

    Article  Google Scholar 

  14. Fan X et al. A solution for at-speed test based on internal PLL. Journal of Computer-Aided Design & Computer Graphics, Mar. 2007, 19(3): 366–370. (In Chinese)

    Google Scholar 

  15. Furukawa H, Wen X, Wang L T, Sheu B, Jiang Z. Wu S. A novel and practical control scheme for inter-clock at-speed testing. In Proc. Int. Test Conf. (ITC 06), Santa Clara, CA, USA, IEEE CS Press, 2006, paper 17.2.

  16. Hatayama K, Nakao M, Sato Y. At-speed built-in test for logic circuits with multiple clocks. In Proc. Asia Test Symp., Guam, USA, 2002, pp.18–20.

  17. Fan X et al. An on-chip test clock control scheme for multi-clock at-speed testing. In Proc. Asia Test Symp. (ATS 07), Beijing, China, IEEE CS Press, 2007, pp.341–348.

  18. Cheng K T, Krstic A. Current directions in automatic test-pattern generation. Computer, Nov. 1999, 32(11): 58–64.

    Article  Google Scholar 

  19. International Technology Roadmap for Semiconductors (ITRS). http://www.itrs.net.

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Authors and Affiliations

  1. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Da Wang, Yu Hu, Hua-Wei Li & Xiao-Wei Li

  2. Graduate University of Chinese Academy of Sciences, Beijing, 100049, China

    Da Wang

Authors
  1. Da Wang
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  2. Yu Hu
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  3. Hua-Wei Li
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  4. Xiao-Wei Li
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Corresponding author

Correspondence to Xiao-Wei Li.

Additional information

This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010, and in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605, and in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476.

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Wang, D., Hu, Y., Li, HW. et al. Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23, 1037–1046 (2008). https://doi.org/10.1007/s11390-008-9193-0

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  • DOI: https://doi.org/10.1007/s11390-008-9193-0

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