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Research Progress of UniCore CPUs and PKUnity SoCs

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Abstract

CPU and System-on-Chip (SoC) are two key technologies of IT industry. During the course of ten years of research, we have defined the UniCore instruction set architecture, and designed the UniCore CPU and the PKUnity SoC family. This cross-disciplinary practice has also fostered many innovations in microprocessor architecture, optimizing compilers, low power design, functional verification, physical design, and so on. In the mean time, we have put technology transfer on the list of our top priorities. This effort has led to several marketable products, such as ultra mobile personal computers, secure micro-workstations and 3C-converged consumer electronics. The development of the next generation products, the 64-bit multi-core CPU and SoC, is also underway. They will find their applications in secure and adaptable computers for mobile and desktop, as well as personal digital multimedia devices. Being consistent with the philosophy and the long-term plan, and by leveraging the cutting-edge process technology, we will continue to make more innovations in CPUs and SoCs, and strengthen our commitment to technology transfer.

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References

  1. Asanovic K, Bodik R et al. The Parallel Computing Laboratory at U.C. Berkeley: A research agenda based on the Berkeley view. Technical Report, UCB/EECS-2008-23, EECS Department, University of California at Berkeley, March 21, 2008.

  2. Slingerland N, Smith A J. Measuring the performance of multimedia instruction sets. IEEE Transactions on Computers, Nov. 2002, 51(11): 1317-1332.

    Article  MathSciNet  Google Scholar 

  3. Vajapeyam S, Valero M. Early 21st century processors. IEEE Computer, Apr. 2001, 34(4): 47-50.

    Google Scholar 

  4. International technology roadmap for semiconductors. http://www.itrs.net, 2008.

  5. Agerwala T, Chatterjee S. Computer architecture: Challenges and opportunities for the next decade. IEEE Micro, May-June, 2005, 25(3): 58-69.

    Article  Google Scholar 

  6. Flynn M J, Hung P. Microprocessor design issues: Thoughts on the road ahead. IEEE Micro, May-June, 2005, 25(3): 16-31.

    Article  Google Scholar 

  7. Asanovic K, Bodik R et al. The landscape of parallel computing research: A view from Berkeley. Technical Report, UCB/EECS-2006-183, EECS Department, University of California at Berkeley, Dec. 18, 2006.

  8. Mobile Intel® Atom™ processor N270 single core datasheet. Intel Corporation, May 2008.

  9. VIA NanoTM processor introductory white paper. VIA Technologies Inc., May 2008.

  10. NVIDIA Corporation. http://www.nvidia.com/object/producttegra apx us.html, 2009.

  11. Sun H, Yang K, Zhao Y, Tong D, Cheng X. CASA: A new IFU architecture for power-efficient instruction cache and TLB designs. Journal of Computer Science and Technology, Jan. 2008, 23(1): 141-153.

    Article  Google Scholar 

  12. Sun H, Tong D, Yuan P, Cheng X. Cluster-based power management mechanism for register files. Acta Electronica Sinica, Feb. 2008, 36(2): 278-284. (in Chinese)

    Google Scholar 

  13. Song C, Cheng X. Multi-level TLB performance evaluation based on Unity-863 SoC. Acta Electronica Sinica, Feb. 2005, 33(2): 363-366. (in Chinese)

    Google Scholar 

  14. Zhao Y, Li X, Tong D, Cheng X. An energy-efficient instruction scheduler design with two-level shelving and adaptive banking. Journal of Computer Science and Technology, Jan. 2007, 22(1): 15-24.

    Article  Google Scholar 

  15. Zhao Y, Li X, Tong D, Sun H, Chen J, Cheng X. Active-cycle based register file design for reduced ports and energy. Chinese Journal of Computers, Feb. 2008, 31(2): 299-308. (in Chinese)

    Article  Google Scholar 

  16. Wang X, Tong D, Sun H, Cheng X. An on-demand mechanism for data cache leakage power management. Acta Electronica Sinica, Feb. 2009, 37(2): 362-366. (in Chinese)

    Google Scholar 

  17. Xu Junjuan. Research on multi-bitwidth and multi-voltage high-level synthesis [Ph.D. Dissertation]. Peking University, 2005.

  18. Zhao X. Leakage power estimation and optimization for standard cell based CMOS circuits [Ph.D. Dissertation]. Peking University, 2007.

  19. Zhou Z. The design and implementation of verification platform of PKUnity863 SoC [Master Thesis]. Peking University, 2007.

  20. Feng Y, Zhou Z, Tong D, Cheng X. Clock domain crossing fault model and coverage metric for validation of SoC design. In Proc. Conference on Design, Automation and Test in Europe, Nice, France, April 16-20, 2007, pp.1385-1390.

  21. Feng Y, Yi J, Liu D, Tong D, Cheng X. Model checking on clock domain crossing design of system-on-chip. Acta Electronica Sinica, May 2008, 36(5): 886-892. (in Chinese)

    Google Scholar 

  22. Feng Y, Xu J, Yi J, Tong D, Cheng X. Property generation method for model checking on clock domain crossing design. Acta Electronica Sinica, Feb. 2009, 37(2): 258-265. (in Chinese)

    Google Scholar 

  23. Yi J. Research on coverage metrics and automatic generation of simulation vectors in SoC functional verification [Ph.D. Dissertation]. Peking University, 2007.

  24. Wang K, Duan L, Cheng X. ExtensiveSlackBalance: An approach to make front-end tools aware of clock skew scheduling. In Proc. the 43rd Design Automation Conference, San Francisco, USA, July 24-28, 2006, pp.951-954.

  25. Wang K, Fang H, Xu H, Cheng X. A fast incremental clock skew scheduling algorithm for slack optimization. In Proc. Asia and South Pacific Design Automation Conference, Seoul, Korea, Jan. 21-24, 2008, pp.492-497.

  26. Duan L. Wire length and power optimization in clock tree routing algorithms [Ph.D. Dissertation]. Peking University, 2008.

  27. Fang H, Tong C, Yao B, Song X, Cheng X. CacheCompress: A novel approach for test data compression with cache for IP embedded cores. In Proc. Int. Conference on Computer-Aided Design, San Jose, USA, Nov. 5-8, 2007, pp.509-512.

  28. Fang H, Tong C, Cheng X. RunBasedReordering: A novel approach for test data compression and scan power. In Proc. Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 23-26, 2007, pp.732-737.

  29. Qu N, Zhao Y, Guan X, Cheng X. A retargetable full system simulator for thin client platform. Chinese Journal of Electronics, Jul. 2007, 16(3): 401-405.

    Google Scholar 

  30. Yang C, Niu Y, Xia Y, Cheng X. Performance analysis applications in virtual of interactive desktop machine environment. Chinese Journal of Electronics, 2008, 17(2): 242-246.

    Google Scholar 

  31. Yang C. Study on several key issues of network computer/server computing [PhD Dissertation]. Peking University, 2007.

  32. Guan X, Liu S, Cheng X. Multiple-interface operating systems designed for thin-client platforms. Chinese Journal of Electronics, 2007, 16(2): 227-230.

    Google Scholar 

  33. Zhu D, Cheng X, Shen H. Dynamic branch prediction research and design for UNICORE architecture. Acta Electronica Sinica, Aug. 2004, 32(8): 1351-1355. (in Chinese)

    Google Scholar 

  34. Zhu D. Research on branch mechanism for UNICORE architecture [Ph.D. Dissertation]. Peking University, 2004.

  35. Liu X, Yang Y, Zhang J, Cheng X. A basic-block reordering algorithm based on structural analysis. Journal of Software, Jul. 2008, 19(7): 1603-1612. (in Chinese)

    Article  Google Scholar 

  36. Slingerland N T, Smith A J. Design and characterization of the Berkeley multimedia workload. Technical Report, UCB/CSD-00-1122, EECS Department, University of California at Berkeley, Dec. 2000.

  37. Chen F, Jiang S, Zhang X. SmartSaver: Turning flash drive into a disk energy saver for mobile computers. In Proc. Int. Symp. Low Power Electronics and Design, Tegernsee, Germany, Oct. 4-6, 2006, pp.412-417.

  38. Kgil T, Mudge T. FlashCache: A NAND flash memory file cache for low power web servers. In Proc. the Int. Conference on Compilers, Architecture and Synthesis for Embedded Systems, Seoul, Korea, Oct. 22-25, 2006, pp.103-112.

  39. Kim Y J, Kwon K T, Kim J. Energy-efficient file placement techniques for heterogeneous mobile storage systems. In Proc. the Int. Conference on Embedded Software, Seoul, Korea, Oct. 22-25, 2006, pp.171-177.

  40. Zadok E, Badulescu I. A stackable file system interface for Linux. In Proc. the 5th Annual Linux Expo, Raleigh, USA, May 18-22, 1999, pp.141-151.

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Authors and Affiliations

  1. Microprocessor Research and Development Center, Peking University, Beijing, 100871, China

    Xu Cheng (Senior Member, CCF), Xiao-Yin Wang, Jun-Lin Lu, Jiang-Fang Yi, Dong Tong, Xue-Tao Guan, Feng Liu, Xian-Hua Liu (Member, CCF), Chun Yang & Yi Feng

Authors
  1. Xu Cheng
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  2. Xiao-Yin Wang
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  3. Jun-Lin Lu
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  4. Jiang-Fang Yi
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  5. Dong Tong
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  6. Xue-Tao Guan
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  7. Feng Liu
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  8. Xian-Hua Liu
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  9. Chun Yang
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  10. Yi Feng
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Corresponding author

Correspondence to Xu Cheng.

Additional information

Supported by the National High Technology Research and Development 863 Program of China under Grant Nos. 2002AA1Z1010, 2003AA1Z1010, 2004AA1Z1010 and 2006AA010202.

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Cheng, X., Wang, XY., Lu, JL. et al. Research Progress of UniCore CPUs and PKUnity SoCs. J. Comput. Sci. Technol. 25, 200–213 (2010). https://doi.org/10.1007/s11390-010-9317-1

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