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A Robust and Power-Efficient SoC Implementation in 65 nm

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Abstract

Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117 mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

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Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao & Dong-Mei Wu

  2. University of Chinese Academy of Sciences, Beijing, 100049, China

    Bin Xiao, Yi-Fu Zhang & Yan-Ping Gao

  3. Loongson Technology Corporation Limited, Beijing, 100190, China

    Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu & Bao-Xia Fan

Authors
  1. Bin Xiao
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  2. Yi-Fu Zhang
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  3. Yan-Ping Gao
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  4. Liang Yang
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  5. Dong-Mei Wu
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  6. Bao-Xia Fan
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Corresponding author

Correspondence to Bin Xiao.

Additional information

This work is supported by the National Natural Science Foundation of China under Grant Nos. 61003064, 61050002, 61070025, 61100163, the National High Technology Research and Development 863 Program of China under Grant Nos. 2012AA010901, 2012AA011002, 2012AA012202, 2013AA014301.

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Xiao, B., Zhang, YF., Gao, YP. et al. A Robust and Power-Efficient SoC Implementation in 65 nm. J. Comput. Sci. Technol. 28, 682–688 (2013). https://doi.org/10.1007/s11390-013-1368-7

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  • DOI: https://doi.org/10.1007/s11390-013-1368-7

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