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Prevention from Soft Errors via Architecture Elasticity

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Abstract

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures holistically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

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Authors and Affiliations

  1. State Key Lab of Computer Architecture and Microprocessor Research Center, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Yi-Xiao Yin & Tian-Shi Chen

  2. University of Chinese Academy of Sciences, Beijing, 100049, China

    Yi-Xiao Yin

  3. Loongson Technology Corporation Limited, Beijing, 100190, China

    Yi-Xiao Yin

  4. IBM Research-China, Beijing, 100193, China

    Qi Guo

Authors
  1. Yi-Xiao Yin
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  2. Yun-Ji Chen
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  3. Qi Guo
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  4. Tian-Shi Chen
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Corresponding author

Correspondence to Yi-Xiao Yin.

Additional information

This work is supported by the National Science and Technology Major Project under Grant Nos. 2009ZX01028-002-003, 2009ZX01029-001-003, the National Natural Science Foundation of China under Grant Nos. 61221062, 61100163, 61133004, 61232009, 61222204, 61221062, 61303158, the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No. XDA06010403, and the Ten Thousand Talent Program of China.

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Yin, YX., Chen, YJ., Guo, Q. et al. Prevention from Soft Errors via Architecture Elasticity. J. Comput. Sci. Technol. 29, 247–254 (2014). https://doi.org/10.1007/s11390-014-1427-8

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  • DOI: https://doi.org/10.1007/s11390-014-1427-8

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