Skip to main content
SpringerLink
Log in

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing

  • Regular Paper
  • Published:
Journal of Computer Science and Technology Aims and scope Submit manuscript

Abstract

The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage (NTV) technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator (VR) aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers 1x and 1.3x higher power conversion efficiency (PCE) than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Esmaeilzadeh H, Blem E, Amant R S, Sankaralingam K, Burger D. Dark silicon and the end of multicore scaling. In Proc. ISCA, June 2011, pp.365-376.

  2. Intel. Enhanced Intel® SpeedStep® Technology for the Intel® Pentium® M Processor. http://download.intel.com/design/network/papers/30117401.pdf, Aug. 2015.

  3. Rotem E, Naveh A, Rajwan D, Ananthakrishnan A, Weissmann E. Power management architecture of the 2nd generation Intel® CoreTM microarchitecture, formerly codenamed Sandy Bridge. http://120.52.72.36/www.hotchips.org/c3pr90ntcsf0/wp-content/uploads/hc_archives/-hc23/HC23.19.9-Desktop-CPUs/HC23.19.921.SandyBridge_Power_10-Rotem-Intel.pdf, August 2011.

  4. Dreslinski R G, Wieckowski M, Blaauw D et al. Nearthreshold computing: Reclaiming Moore’s law through energy efficient integrated circuits. Proceedings of the IEEE, 2010, 98(2): 253–266.

    Article  Google Scholar 

  5. Kim J, Horowitz M. An efficient digital sliding controller for adaptive power-supply regulation. IEEE Journal of Solid-State Circuits (JSSC), 2002, 37(5): 639–647.

    Article  Google Scholar 

  6. Jain S, Khare S, Yada S et al. A 280mV-to-1.2V wideoperating-range IA-32 processor in 32nm CMOS. In Proc. IEEE ISSCC, Feb. 2012, pp.66-68.

  7. Esmaeilzadeh H, Blem E, Amant R S, Sankaralingam K, Burger D. Power limitations and dark silicon challenge the future of multicore. ACM Transactions on Computer Systems (TOCS), 2012, 30(3): 11:1–11:27.

  8. Le H P, Sanders S R, Alon E. Design techniques for fully integrated switched-capacitor DC-DC converters. IEEE Journal of Solid State Circuits (JSSC), 2011, 46(9): 2120–2131.

    Article  Google Scholar 

  9. Schrom G, Hazucha P, Paillet F, Gardner D S, Moon S T, Karnik T. Optimal design of monolithic integrated DC-DC converters. In Proc. IEEE ICICDT, May 2006.

  10. Kim W, Gupta M S, Wei G Y, Brooks D. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proc. the 14th HPCA, Feb. 2008, pp.123-134.

  11. Choi Y, Chang N, Kim T. DC-DC converter-aware power management for low-power embedded systems. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 2007, 26(8): 1367–1381.

    Article  Google Scholar 

  12. Amelifard B, Pedram M. Design of an efficient power delivery network in an SoC to enable dynamic power management. In Proc. ACM/IEEE ISLPED, August 2007, pp.328-333.

  13. Cho Y, Kim Y, Joo Y, Lee K, Chang N. Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling. In Proc. ACM/IEEE ISLPED, August 2008, pp.309-314.

  14. Zumel P, Fernandez C, de Castro A, Garcia O. Efficiency improvement in multiphase converter by changing dynamically the number of phases. In Proc. the 37th PESC, June 2006.

  15. Li S, Ahn J H, Strong R D, Brockman J B, Tullsen D M, Jouppi N P. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proc. the 42nd Annual IEEE/ACM MICRO, Dec. 2009, pp.469-480.

  16. Bienia C, Kumar S, Singh J P, Li K. The PARSEC benchmark suite: Characterization and architectural implications. In Proc. the 17th PACT, October 2008, pp.72-81.

  17. Gunther S, Deval A, Burton T, Kumar R. Energy-efficient computing: Power management system on the Nehalem family of processors. Intel Technology Journal, 2010, 14(3): 50–65.

    Google Scholar 

  18. Yan G, Li Y, Han Y, Li X, Guo M, Liang X. AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. In Proc. the 18th IEEE HPCA, Feb. 2012, pp.287-298.

  19. Ng V, Sanders S. A 92%-efficiency wide-input-voltagerange switched-capacitor DC-DC converter. In Proc. IEEE ISSCC, Feb. 2012, pp.282-284.

  20. KimW, Brooks D, Wei G Y. A fully-integrated 3-level DCDC converter for nanosecond-scale DVFS. IEEE Journal of Solid State Circuits (JSSC), 2012, 47(1): 206–219.

    Article  Google Scholar 

  21. He X, Yan G, Han Y, Li X. SuperRange: Wide operational range power delivery design for both STV and NTV computing. In Proc. DATE, March 2014.

  22. Sinkar A A,Wang H, Kim N S. Workload-aware voltage regulator optimization for power efficient multi-core processors. In Proc. DATE, March 2012, pp.1134-1137.

  23. Amelifard B, Pedram M. Optimal selection of voltage regulator modules in a power delivery network. In Proc. the 44th ACM/IEEE DAC, June 2007, pp.168-173.

  24. Ghasemi H R, Sinkar A A, Schulte M J, Kim N S. Costeffective power delivery to support per-core voltage domains for power-constrained processors. In Proc. the 49th ACM/IEEE DAC, June 2012, pp.56-61.

  25. Yan G, Han Y, Liu H, Liang X, Li X. MicroFix: Exploiting path-grained timing adaptability for improving powerperformance efficiency. In Proc. ACM/IEEE ISLPED, August 2009, pp.395-400.

  26. Han Y, Wang Y, Li H, Li X. Enabling near-threshold voltage (NTV) operation in multi-VDD cache for power reduction. In Proc. IEEE ISCAS, May 2013, pp.337-340.

Download references

Author information

Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Xin He, Gui-Hai Yan, Yin-He Han & Xiao-Wei Li

  2. University of Chinese Academy of Sciences, Beijing, 100049, China

    Xin He

Authors
  1. Xin He
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Gui-Hai Yan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yin-He Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Xiao-Wei Li
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Xin He.

Additional information

This work is supported by the National Natural Science Foundation of China under Grant Nos. 61572470, 61532017, 61522406, 61432017, 61376043, and 61221062.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

He, X., Yan, GH., Han, YH. et al. Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. J. Comput. Sci. Technol. 31, 253–266 (2016). https://doi.org/10.1007/s11390-016-1625-7

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11390-016-1625-7

Keywords

Search

Navigation