Abstract
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a (n, n−1, m, 3) convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit (X bit). When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.
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References
Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 1999.
Xiang, D., Gu, S., Sun, J., Wu, Y., A cost-effective scan architecture for scan testing with non-scan test power and test application cost, in Proc. of Design Automation Conference, New Orleans: ACM Press, 2003, 744–747.
Ivanov, A., Tsuji, B., Zorian, Y., Programmable space compactors for BIST, IEEE Transactions on Computers, 1996, 45(12): 1393–1405.
Chakrabarty, K., Murray, B. T., Hays, J. P., Optimal zero-aliasing space compaction of test responses, IEEE Transactions on Computers, 1998, 47(11): 1171–1187.
Bhattacharya, B. B., Dmitriev, A., Goessel, M., Zero-aliasing space compaction of test responses using a single periodic output, IEEE Transactions on Computers, 2003, 52(12): 1646–1651.
Wohl, P., Waicukauski, J. A., Williams, T. W., Design of compactors for signature-analyzers in built-in self-test, in Proc. of International Test Conference, Baltimore: IEEE Press, 2001, 54–63.
Barnhart, C., Brunkhorst, V., Distler, F. et al., Extending OPMISR beyond 10x scan test efficiency, IEEE Design & Test of Computers, 2002, 19(5): 65–73.
Wohl, P., Huisman, L., Analysis and design of optimal combinational compactors, in Proc. of VLSI Test Symposium, Napa Valley: IEEE Press, 2003, 101–106.
Saluja, K. K., Karpovsky, M., Testing computer hardware through data compression in space and time, in Proc. of International Test Conference, Philadelphia: IEEE Press, 1983, 83–88.
Mitra, S., Kim, K. S., X-Compact: An Efficient Response Compaction Technique, IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, 2004, 23(3): 421–432.
Patel, J. H., Lumetta, S. S., Reddy, S. M., Application of Saluja-Karpovsky compactors to test responses with many unknowns, in Proc. of VLSI Test Symposium, Napa Valley: IEEE Press, 2003, 107–112.
Lumetta, S. S., Mitra, S., X-codes: Error control with unknowable inputs, in Proc. of International Symposium on Information Theory, Pacifico: IEEE Press, 2003, 102.
Wang, C., Reddy, S. M., Pomeranz, I. et al., On compacting test response data containing unknown values, in Proc. of International Conference on Computer-Aided Design, San Jose: IEEE Press, 2003, 855–862.
Pomeranz, I., Kundu, I. S., Reddy, S. M., On output response compression in the presence of unknown output values, in Proc. of Design Automation Conference, New Orleans: IEEE Press, 2002, 255–258.
Rajski, J., Tyszer, J., Wang, C., Reddy, S. M., Convolutional compaction of test responses, in Proc. of International Test Conference, Charlotte: IEEE Press, 2003, 745–754.
Han, Y., Xu, Y., Li, H. et al., Test resource partitioning based on efficient responses compaction for test time and tester channels reduction, in Proceedings of Asian Test Symposium, Xi’an: IEEE Press, 2003, 440–445.
Elias, P., Coding for Noisy Channels, IRE Internsational Convention Record, 1955, 37–46.
Forney, G. D., Convolutional codes I: Algebraic Structure, IEEE Transactions on Information Theory, 1970, 16: 720–738.
Luerssen, H. G., Schmale, W., Distance bounds for convolutional codes and some optimal codes, in the Report available at http://www.uni-oldenburg.de/math/personen/gluesing/OptCodes.pdf.
Brualdi, R. A., Introductory Combinatorics, 3rd ed., New Jersey, Pearson Education, Inc, 1999.
Lee, H. K., Ha, D. S., HOPE: An efficient parallel fault simulator for synchronous sequential circuits, in Proc. of Design Automation Conference, Anaheim: IEEE Press, 1992, 336–340.
Hamzaoglu, I., Patel, J. H., Test set compaction algorithms for combinational circuits, in Proc. of IEEE International Conference on Computer-Aided Design, San Jose: IEEE Press, 1998, 283–289.
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Han, Y., Li, H., Li, X. et al. Response compaction for system-on-a-chip based on advanced convolutional codes. SCI CHINA SER F 49, 262–272 (2006). https://doi.org/10.1007/s11432-006-0262-0
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DOI: https://doi.org/10.1007/s11432-006-0262-0