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Planar split dual gate MOSFET

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Abstract

A new planar split dual gate (PSDG) MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage (V t) and sub-threshold swing (SS), as well as the device saturated current. The PSDG MOSFET transistor leakage current (Ioff) can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.

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References

  1. http://www.itrs.net/Links/2001ITRS/PIDS.pdf

  2. Hu C, Device challenges and opportunities. Symposium on VLSI Tech Digest of Techical Papers, 2004, 4–5

  3. Chau, R, Kavalieros J, Roberds B, et al. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays. IEDM, 2000, 45–48

  4. Mathew L, Yang D, Kalpat S, et al. Multiple independent gate field effect transistor (MIGFET)-multi-Fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics, 2005 Symposium on VLSI Tech Digest of Technical Papers, Kyoto, 2005, 200–201

  5. Park T, Choi S, Lee D H, et al. Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers. Symposium on VLSI Tech Digest of Technical Papers, Kyoto, 2003, 10A-3

  6. Doyle B, Boyanov B, Datta S, et al. Tri-gate fully-depleted CMOS transistors: fabrication, design and layout. Symposium on VLSI Technology Digest of Technical Papers, Kyoto, 2003, 10A-2

  7. Sze S M. Semiconductor Devices. New York: John Wiley & Sons Inc., 2002

    Google Scholar 

  8. Pei G, Ni W P, Abhishek V K, et al. A physical compact model of DG MOSFET for mixed-signal circuit applications—Part I: Model description. IEEE Trans on Ed, 2003, 50(10): 2135–2143

    Google Scholar 

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Authors and Affiliations

  1. Memory Technology Development Center, Semiconductor Manufacturing International (Shanghai) Corp., Shanghai, 201203, China

    DeYuan Xiao, Gary Chen, Roger Lee, Yung Liu & ChiCheong Shen

Authors
  1. DeYuan Xiao
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  2. Gary Chen
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  3. Roger Lee
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  4. Yung Liu
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  5. ChiCheong Shen
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Correspondence to DeYuan Xiao.

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Xiao, D., Chen, G., Lee, R. et al. Planar split dual gate MOSFET. Sci. China Ser. F-Inf. Sci. 51, 440–448 (2008). https://doi.org/10.1007/s11432-008-0027-z

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  • DOI: https://doi.org/10.1007/s11432-008-0027-z

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