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Novel electrical characterization for advanced CMOS gate dielectrics

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Abstract

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: 1) inelastic electron tunneling spectroscopy (IETS), 2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

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Authors and Affiliations

  1. Department of Electrical Engineering, Yale University, New Haven, CT, 06520, USA

    T. P. Ma

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  1. T. P. Ma
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Correspondence to T. P. Ma.

Additional information

Supported by the Semiconductor Research Corporation and the U.S. National Science Foundation (Grant No. MRSEC DMR 0520495)

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Ma, T.P. Novel electrical characterization for advanced CMOS gate dielectrics. Sci. China Ser. F-Inf. Sci. 51, 774–779 (2008). https://doi.org/10.1007/s11432-008-0068-3

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  • DOI: https://doi.org/10.1007/s11432-008-0068-3

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