Abstract
A new generation architecture of IP routers called massive parallel forwarding and switching (MPFS) is proposed, which is totally different from modern routers. The basic idea of MPFS is mapping complicated forwarding process into multilevel scalable switch fabric so as to implement packet forwarding in a pipelining and distributed way. This processing mechanism is named forwarding in switching (FIS). By interconnecting multi-stage, lower speed components, called forwarding and switching nodes (FSN), MPFS achieves better scalability in forwarding and switching performance just like MPP. We put emphasis upon IPv6 lookup problem in MPFS and propose a method for partitioning IPv6 FIB and mapping them to switch fabric. Simulation and computation results suggest that MPFS routers can support line-speed forwarding with a million of IPv6 prefixes at 40 Gbps. We also propose an implementation of 160 Tbps core router based on MPFS architecture at last.
Similar content being viewed by others
References
Cisco products datasheet. Cisco Carrier Routing System: Many Services, One Network, Limitless Possibilities. http://www.cisco. com/en/US/prod/collateral/routers/ps5763/prodbrochure0900aecd800f8118.pdf
NANOG reports. Pushing the FIB limits, perspectives of the pressures confronting modern routers. http://www.nanog.org/ mtg-0702/presentations/bof-report.pdf
Gupta M, Singh S. Greening of the Internet. In: Proceedings of the 2003 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications. 2003. 19–26
Christensen K J, Nordman B, George A D. The next frontier for communications networks: power management. Comp Commun, 2004, 27(18): 1758–1770
Meyer D, Zhang L, Fall K. Report from the IAB Workshop on Routing and Addressing. IETF RFC4984, September 2007
Turner J S, Taylor D E. Diversifying the Internet. In: Proceedings of the Global Telecommunications Conference. 2005. 1110–1123
Gripp J, Stiliadis D, Simsarian J E, et al. IRIS optical packet router. J Opt Netw, 2006, 5(8): 589–597
Yang L, Dantu D. Forwarding and control element separation (ForCES) framework. IETF RFC3746, April 2004
Sapountzis G, Katevenis M. Benes switching fabrics with O(n)-complexity internal backpressure. IEEE Commun Mag, 2005, 43(1): 88–94
Turner J, Yamanaka N. Architectural choices in large scale ATM switches. IEICE Trans Commun, 1998, E81-B(2):120–137
Chao H J, Liew S Y, Jing Z G. A dual-level matching algorithm for 3-stage Clos-network packet switches. In: Proceedings of the 11th Symposium on High Performance Interconnects. 2003. 38–43
Aslam A, Christensen K J. A parallel packet switch with multiplexors containing virtual input queues. Comp Commun, 2004, 27: 1248–1263
Keslassy I, Chuang S T, Yu K, et al. Scaling Internet routers using optics. In: Proceedings of the 2003 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications. 2003. 189–200
Semeria C. T-series routing platforms: System and packet forwarding architecture. http://arl.wustl.edu/:_jst/cse/577/readings/juniperTseries.pdf
Sherwood T, Varghese G, Calder B. A pipelined memory architecture for high throughput network processors. In: Proceedings of the 30th International Symposium on Computer Architecture. 2003. 288–299
Eatherton W, Varghese G, Dittia Z. Tree Bitmap: Hardware/software IP lookups with incremental updates. ACM SIGCOMM Comp Commun Rev, 2004, 34(2): 97–122
Shreedhar M, Varghese G. Efficient fair queuing using deficit round-robin. IEEE/ACM Trans Netw, 1996, 4(3): 375–385
Chung F, Graham R, Varghese G. Parallelism versus memory allocation in pipelined router forwarding engines. In: SPAA, 2004, Barcelona, Spain
Basu A, Narlikar G. Fast incremental updates for pipelined forwarding engines. IEEE/ACM Trans Netw, 2005, 13(3):690–703
Shah D, Iyer S, Prabhakar B, et al. Maintaining statistics counters in router line cards. IEEE Micro, 2002, Jan–Feb: 76–81
Ramabhadran S, Varghese G. Efficient implementation of a statistics counter architecture. In: SIGMETRICS, 2003, San Diego, California, USA
Epps G, Tsiang D, Boures T. System power chattenges. www.cisco.com/web/about/ac50/ac207/proceedings/POWER_GEPPS_rev3.ppt
Harsha N, Ramesh G, George V. The impact of address allocation and routing on the structure and implementation of routing tables. In: Proceedings of the 2003 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications. 2003. 125–136
Wang M, Deering S, Hain T. Non-random generator for IPv6 tables. In: IEEE Symposium on High Performance Interconnects, 2004. 35–40
CERNET2 reports. Ipv6 FIB Prefix Length Distribution. http://bgpview.6test.edu.cn/datav6
Author information
Authors and Affiliations
Corresponding author
Additional information
Supported by the National Basic Research Program of China (973 Program) (Grant No. 2003CB314802)
Rights and permissions
About this article
Cite this article
Sun, Z., Dai, Y. & Gong, Z. MPFS: A truly scalable router architecture for next generation Internet. Sci. China Ser. F-Inf. Sci. 51, 1761–1771 (2008). https://doi.org/10.1007/s11432-008-0148-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-008-0148-4