Abstract
Side channel attacks (SCAs) on security software and hardware have become major concerns on computer and system security. The existing SCAs generally require the knowledge of the corresponding cryptographic algorithm and implementation adopted in the target; therefore, they are not fully suitable for practical applications. In this paper, we propose a novel SCA—polar differential power attack (polar DPA). We found that DPA peaks have different biases for different cryptographic algorithms and implementations. Based on these biases, we can successfully attack a block cipher, assuming that the cipher algorithm uses a secret key in its first round, without the knowledge of the cipher algorithm or implementation. Other rounds can be treated as a black box. We present a detailed theoretical analysis and experiment to demonstrate the correctness and efficiency of our scheme. Furthermore, our scheme has demonstrated an improvement over the leakage evaluation scheme due to Ichikawa et al. (CHES 2005). Our evaluation method can be used in electronic design automatic (EDA) flows and can help security circuit designers to understand the data leakage due to SCAs.
Similar content being viewed by others
References
Kocher P. Timings attacks on implementations of diffie hellman, rsa, dss and other systems. In: Crypto 1996. Berlin: Springer-Verlag, 104–113
Shamir A, Biham E. Differential fault analysis of secret key cryptosystems. In: Proceedings of Crypto’97, 1998. Berlin: Springer-Verlag. LNCS 1294. 513–525
Jun B, Kocher P, Jaffe J. Differential power analysis. In: Crypto 1999. LNCS 1666. 338–397
Sloan R H, Messerges T S, Dabbish E A. Investigations of power analysis attacks on smart cards. In: Proceedings of the USENIX Workshop on Smartcard Technology (WOST 1999). Berkeley: USENIX Association Berkeley, 1999. 17–28
Messerges T S. Using second order power analysis to attack dpa resistant software. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000), 2000. LNCS 1965. 238–251
Mayer S R. Smartly analyzing the simplicity and the power of simple power analysis on smart cards. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000), 2000. LNCS 1965. 78–92
Joye M, Yen S M. Checking before output may not be enough against fault-based cryptanalysis. In: IEEE Trans Comput, 2000, 49 967–970
Rao J R, Rohatgi P, Agrawal D, et al. The em side-channels(s): Attacks and assessment methodologies. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2002), 2003. LNCS 2523. 29–45
Avanzi R M. Countermeasures against differential power analysis for hyperelliptic curve cryptosystems. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003), 2004. LNCS 2779, 366–381
Quisquater J J, Kim C H. New differential fault analysis on aes key schedule: Two faults are enough. In: Eighth Smart Card Research and Advanced Application Conference CARDIS 2008, 2008. LNCS 5189. 48–62
Olivieri M, Trifiletti A, Menichelli F, et al. High-level side-channel attack modeling and simulation for security-critical systems on chips. In: IEEE Trans Dependable Secur Comput, 2008, 5. 164–176
Feng D, Zhou Y. Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing. 2005. http://eprint.iacr.org/2005/388/
Schaumont P, Tiri K. Masking and dual-rail logic don’t add up. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), 2007. LNCS 4727. 95–106
Ichikawa T, Suzuki D, Saeki M. Dpa leakage models for cmos logic circuits. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), 2005. LNCS 3659. 366–382
Standaert F X, Veyrat-Charvillon N. Mutual information analysis: How, when and why? In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), 2009. LNCS 5747. 429–443
Ichikawa T, Suzuki D, Saeki M. Random switching logic: A countermeasure against dpa based on transition probability. Cryptology ePrint Archive Report 2004, 346. http://eprint.iacr.org/2004/346.pdf
Verbauwhede I, Tiri K. A logic level design methodology for a secure dpa resistant asic or fpga implementation. In: Design, Automation and Test in Europe Conference (DATE 2004), 2004. 246–251
Güneysu T, Paar C, Burleson W, et al. Trojan side-channels: Lightweight hardware trojans through side-channel engineering. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), 2009. LNCS 5747. 382–395
Shimizu K, Satoh A, Saeki M, et al. A design methodology for a dpa-resistant cryptographic lsi with rsl techniques. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), 2009. LNCS 5747. 189–204
Pietrzak K, Dziembowski S. Leakage-resilient cryptography in the standard model. http://eprint.iacr.org/2008/240.pdf
Charvillon N V, Renauld M, Standaert F X. Algebraic side-channel attacks on the aes: Why time also matters in dpa. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), 2009. LNCS 5747. 99–111
Zhang H G, Li C L, Tang M. Capability of evolutionary cryptosystems against differential cryptanalysis. Sci China Inf Sci, 2011, 54: 1991–2000
Zhang H G, Feng X T, Qin Z P, et al. Evolutinary cryptosystems and evolutionary design for DES. J China Institute Commun, 2002, 23: 57–64
Donckers N, Quisquater J J, Peeters E, et al. Improved higher-order side-channel attacks with fpga experiments. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), 2005. LNCS 3659. 309–323
Olivier F, Brier E, Clavier C. Correlation power analysis with a leakage model. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2004), 2004. LNCS 3156. 16–29
Prouff E. Dpa attacks and s-boxes. In: FSE 2005, 2005. LNCS 3557. 424–441
Luzzi R, Trifiletti A, Bucci M, et al. Three-phase dual-rail pre-charge logic. In: Workshop on Cryptographic Hardware and Embedded Systems (CHES 2006), 2006. LNCS 4249. 232–241
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Tang, M., Qiu, Z., Gao, S. et al. Polar differential power attacks and evaluation. Sci. China Inf. Sci. 55, 1588–1604 (2012). https://doi.org/10.1007/s11432-012-4588-5
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11432-012-4588-5